> -Original Message-
> From: Nguyen, Michael H
> Sent: Thursday, December 11, 2014 8:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v7 1/5] drm/i915: Implement a framework for batch buffer
> pools
>
> From: Brad Volkin
>
> This adds a s
> -Original Message-
> From: Nguyen, Michael H
> Sent: Thursday, December 11, 2014 8:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v7 2/5] drm/i915: Use batch pools with the command parser
>
> From: Brad Volkin
>
> This patch sets up all
On 12/12/2014 01:53 AM, Matt Roper wrote:
Once we integrate our work into the atomic pipeline, plane commit
operations will need to happen with interrupts disabled, due to vblank
evasion. Our commit functions today include sleepable work, so those
operations need to be split out and run either b
On Thu, Dec 11, 2014 at 08:17:00AM +, Chris Wilson wrote:
> In order to act as a full command barrier by itself, we need to tell the
> pipecontrol to actually stall the command streamer while the flush runs.
> We require the full command barrier before operations like
> MI_SET_CONTEXT, which cu
> -Original Message-
> From: Nguyen, Michael H
> Sent: Thursday, December 11, 2014 8:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v7 3/5] drm/i915: Use batch length instead of object size in
> command parser
>
> From: Brad Volkin
>
> Pr
On Wed, Dec 10, 2014 at 02:00:02PM -0800, Jesse Barnes wrote:
> Should address a warning reported in #79824.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=79824
> Signed-off-by: Jesse Barnes
Isn's this fixed by https://freedesktop.org/patch/37900/ ?
> ---
> drivers/gpu/drm/i915/
> -Original Message-
> From: Nguyen, Michael H
> Sent: Thursday, December 11, 2014 8:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v7 4/5] drm/i915: Mark shadow batch buffers as purgeable
>
> From: Brad Volkin
>
> By adding a new exec_en
On Fri, Dec 12, 2014 at 11:09:15AM +0200, Ville Syrjälä wrote:
> On Thu, Dec 11, 2014 at 08:17:00AM +, Chris Wilson wrote:
> > In order to act as a full command barrier by itself, we need to tell the
> > pipecontrol to actually stall the command streamer while the flush runs.
> > We require the
On Thu, Dec 11, 2014 at 02:24:53PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 11, 2014 at 08:16:59AM +, Chris Wilson wrote:
> > In the gen7 pipe control there is an extra bit to flush the media
> > caches, so let's set it during cache invalidation flushes.
>
> Bspec is telling me this bit is al
> -Original Message-
> From: Nguyen, Michael H
> Sent: Thursday, December 11, 2014 8:13 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Bloomfield, Jon; Brad Volkin
> Subject: [PATCH v7 5/5] drm/i915: Tidy up execbuffer command parsing code
>
> From: Brad Volkin
>
> Move it to a separate
From: Tim Gore
The android makefiles were passing the -std=c99 flag to the
compiler which disables the typeof keyword. This causes a
build fail for a recent addition to igt_aux.h.
Change this to -std=gnu99, which is the flag used in the
linux build
Signed-off-by: Tim Gore
---
benchmarks/Androi
Gentle reminder for review..
- Vandana
On 10-Nov-14 4:58 PM, Kannan, Vandana wrote:
In the earlier RFC patch series, PPS related code was moved to intel_panel.c
to make it usable for all internal panels. In this patch series, the PPS
related functions are split based on platform in intel_dp.c i
From: Tim Gore
intel_sprite_on wont build on Android, due to use
of a particular API that has changed in Gmin
Signed-off-by: Tim Gore
---
demos/Android.mk | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/demos/Android.mk b/demos/Android.mk
index 6227e06..be7f3c2 100644
On Mon, 10 Nov 2014, Vandana Kannan wrote:
> Calls to setup eDP panel power sequencer were there in dp_init_connector()
> function. Moving these calls to edp_init_connector() to keep all PPS calls
> together and under edp init.
It's a bit tricky, but I think you need to setup the power sequencer
On Mon, 10 Nov 2014, Vandana Kannan wrote:
> vlv_power_sequencer_pipe() calls into init PPS functions. Changing this
> function to make it only return pipe and not call PPS init.
> This is because PPS init calls into this function to get a pipe ID and all
> other callers just need the pipe ID.
>
>
On Fri, Dec 12, 2014 at 09:20:49AM +, Chris Wilson wrote:
> On Fri, Dec 12, 2014 at 11:09:15AM +0200, Ville Syrjälä wrote:
> > On Thu, Dec 11, 2014 at 08:17:00AM +, Chris Wilson wrote:
> > > In order to act as a full command barrier by itself, we need to tell the
> > > pipecontrol to actual
On 12 December 2014 at 10:18, wrote:
> From: Tim Gore
>
> intel_sprite_on wont build on Android, due to use
> of a particular API that has changed in Gmin
>
> Signed-off-by: Tim Gore
> ---
> demos/Android.mk | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/demos/A
From: Tim Gore
intel_sprite_on wont build on Android.
Signed-off-by: Tim Gore
---
demos/Android.mk | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/demos/Android.mk b/demos/Android.mk
index 6227e06..d2592b1 100644
--- a/demos/Android.mk
+++ b/demos/Android.mk
@@ -4,7 +4,9
From: Tim Gore
The android makefiles were passing the -std=c99 flag to the
compiler which disables the typeof keyword. This causes a
build fail for a recent addition to igt_aux.h.
Change this to -std=gnu99, which is the flag used in the
linux build
Signed-off-by: Tim Gore
---
benchmarks/Androi
On 12 December 2014 at 12:14, wrote:
> From: Tim Gore
>
> The android makefiles were passing the -std=c99 flag to the
> compiler which disables the typeof keyword. This causes a
> build fail for a recent addition to igt_aux.h.
> Change this to -std=gnu99, which is the flag used in the
> linux bu
On 12/12/2014 01:54 AM, Matt Roper wrote:
Add the new driver entrypoints that will be called by the atomic plane
helpers.
This patch does not actually switch over to the new plane helpers yet,
so there should be no functional change here. Also note that although
plane programming was already sp
On 12/09/2014 09:53 PM, Matt Roper wrote:
Now that we have hooks to enable the atomic plane helpers, we can use
the plane helpers for our .update_plane() and .disable_plane()
entrypoints.
Note that we still need to make a few small behavioral changes to the
driver entrypoints here as we make the
On 11/13/2014 12:02 PM, Yu Zhang wrote:
With Intel GVT-g, the global graphic memory space is partitioned by
multiple vGPU instances in different VMs. The ballooning code is called
in i915_gem_setup_global_gtt(), utilizing the drm mm allocator APIs to
mark the graphic address space which are part
On 11/13/2014 12:02 PM, Yu Zhang wrote:
With Intel GVT-g, the fence registers are partitioned by multiple
vGPU instances in different VMs. Routine i915_gem_load() is modified
to reset the num_fence_regs, when the driver detects it's running in
a VM. And the allocated fence number is provided in
On 11/13/2014 12:02 PM, Yu Zhang wrote:
Framebuffer compression is disabled when driver detects it's
running in a Intel GVT-g enlightened VM, because FBC is not
emulated and there is no stolen memory for a vGPU.
v2:
take Chris' comments:
- move the code into intel_update_fbc()
Signed-
On 11/13/2014 12:02 PM, Yu Zhang wrote:
Display switch logic is added to notify the host side that
current vGPU have a valid surface to show. It does so by
writing the display_ready field in PV INFO page, and then
will be handled in the host side. This is useful to avoid
trickiness when the VM's
On 11/13/2014 12:02 PM, Yu Zhang wrote:
With Intel GVT-g, GPU power management is controlled by
host driver, so there is no need to provide virtualized
GPU PM support. In the future it might be useful to gather
VM input for freq boost, but now let's disable it simply.
v2:
take Chris' comments:
On 11 December 2014 at 13:11, Joonas Lahtinen
wrote:
> Currently out of tree build fails because the version.h.tmp is generated
> into the source directory instead of the build directory where it is
> later looked for. This commit fixes it.
>
> From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep
On 11/13/2014 12:02 PM, Yu Zhang wrote:
In the virtualized environment, forcewake operations are not
necessory for the driver, because mmio accesses will be trapped
necessary
and emulated by the host side, and real forcewake operations are
also done in the host. New mmio write handlers are a
On 11/13/2014 12:02 PM, Yu Zhang wrote:
The current Intel GVT-g only supports alias ppgtt. And the
emulation is done in the host by first trapping PP_DIR_BASE
mmio accesses. Updating PP_DIR_BASE by using instructions such
as MI_LOAD_REGISTER_IMM are hard to detect and are not supported
in curre
I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
chance to be working as well as prevous platforms.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(
2 pieces of code need to read out the DDI clock: the DDI encoder and the
MST encoder .get_config() vfuncs.
Until now the SKL read out code was only in the former, so let's move
the pre and post SKL logic in intel_ddi_clock_get() and this this one
everywhere.
Signed-off-by: Damien Lespiau
---
dr
The programming seems fairly similar to previous platforms, so let's create the
DP encoders on SKL as well.
--
Damien
Damien Lespiau (2):
drm/i915: Consolidate DDI clock reading out in a single function
drm/i915/skl: Skylake also supports DP MST
drivers/gpu/drm/i915/intel_ddi.c | 13 ++
From: Tim Gore
intel_sprite_on wont build on Android. Previous
attempt to disable was just wrong!
Signed-off-by: Tim Gore
---
demos/Android.mk | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/demos/Android.mk b/demos/Android.mk
index b20d61e..5a00116 100644
--- a/demos
On 12/09/2014 05:29 AM, sonika.jin...@intel.com wrote:
From: Sonika Jindal
The pipe wm parameters is not correctly updated with sprite parameters
because it copies them for each plane from plane_list to the sprite
offset in pipe wm parameters. Since plane_list also contains primary and
cursor
2014-12-04 12:07 GMT-02:00 Imre Deak :
> On Thu, 2014-12-04 at 14:58 +0100, Daniel Vetter wrote:
>> On Thu, Dec 04, 2014 at 02:59:32PM +0200, Imre Deak wrote:
>> > Atm, we don't disable RPS interrupts and related work items before
>> > resetting the GPU. This may interfere with the following GPU
>>
After
commit a18c0af171bfb875012da26f23df051004726973
uthor: Thierry Reding
Date: Wed Dec 10 11:38:49 2014 +0100
drm: Zero out DRM object memory upon cleanup
we will use the eDP encoder during destroying it. Fix this by calling
drm_encoder_cleanup() at a point when the encoder is not used
[PATCH 1/3] drm/i915: use effective_size for ringbuffer calculations
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
[PATCH 2/3] drm/i915: recheck ringspace after wait+retire
When a ringbuffer is nearly ful
In {intel,logical}_ring_wait_request(), we try to find a request
whose completion will release the amount of ring space required.
If we find such a request, we wait for it, and then retire it, in
the expectation that we will now have at least the required amount
of free space in the ring. But it's
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c |5 +++--
2 files changed, 4 insertions(+),
When adding instructions to a legacy or LRC ringbuffer, the sequence of
emit() calls must be preceded by a call to intel(_logical)_ring_begin()
to reserve the required amount of space, and followed by a matching call
to intel(_logical)_ring_advance() (note that this used to trigger
immediate submis
2014-12-08 16:27 GMT-02:00 Mika Kuoppala :
> From: Chris Wilson
>
> Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
> revert the crude hack
>
> commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
> Author: Paulo Zanoni
> Date: Tue Apr 1 14:55:07 2014 -0300
>
> drm/i915: do
On Sat, Dec 13, 2014 at 11:43:27AM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Higher RC6 residency is observed using timeout mode
> instead of EI mode. It's Recommended to use TO Method for RC6.
>
> v2: Add comment about timeout threshold. (Tom)
Yeah if TO is better let's just
A new intel-gpu-tools quarterly release is available with the following changes:
- New test cases added: drm_import_export, gem_gpgpu_fill, gem_ppgtt,
gem_tiled_wb, kms_pwrite_crc.
- New helper for interactive progress indicators (see igt_print_activity and
igt_progress), which can be disable
On Fri, Dec 12, 2014 at 02:22:31PM -0200, Paulo Zanoni wrote:
> 2014-12-08 16:27 GMT-02:00 Mika Kuoppala :
> > From: Chris Wilson
> >
> > Calling intel_runtime_pm_put() is illegal from a soft-irq context, so
> > revert the crude hack
> >
> > commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c
> > Auth
Copy a block into destination object with varying dst/src offsets.
Put guard area before and after the blit target to see that it didn't
touch memory out of blit boundaries.
References: https://bugs.freedesktop.org/show_bug.cgi?id=79053
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
gem_blt_
On 12 December 2014 at 16:53, Mika Kuoppala
wrote:
> Copy a block into destination object with varying dst/src offsets.
> Put guard area before and after the blit target to see that it didn't
> touch memory out of blit boundaries.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=79053
On Fri, Dec 12, 2014 at 05:57:38PM +0200, Imre Deak wrote:
> After
>
> commit a18c0af171bfb875012da26f23df051004726973
> uthor: Thierry Reding
> Date: Wed Dec 10 11:38:49 2014 +0100
>
> drm: Zero out DRM object memory upon cleanup
>
> we will use the eDP encoder during destroying it. Fix
On Fri, Dec 12, 2014 at 04:13:03PM +, Dave Gordon wrote:
> static inline void intel_ring_advance(struct intel_engine_cs *ring)
> {
> struct intel_ringbuffer *ringbuf = ring->buffer;
> - ringbuf->tail &= ringbuf->size - 1;
> +
> + __intel_ringbuffer_check(ringbuf);
> +
> + /*
On 12/12/14 17:12, Chris Wilson wrote:
> On Fri, Dec 12, 2014 at 04:13:03PM +, Dave Gordon wrote:
>> static inline void intel_ring_advance(struct intel_engine_cs *ring)
>> {
>> struct intel_ringbuffer *ringbuf = ring->buffer;
>> -ringbuf->tail &= ringbuf->size - 1;
>> +
>> +__int
On Fri, Dec 12, 2014 at 02:18:15PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> Use new Sideband offset to read max/min/gaur freq based on the SKU it
> is running on. Based on the Number of EU, we read different bits to
> identify the max frequencies at which system can run.
>
> S
2014-12-10 21:53 GMT-02:00 Todd Previte :
> Add the skeleton framework for supporting automation for Displayport
> compliance
> testing. This patch adds the necessary framework for the source device to
> appropriately respond to test automation requests from a sink device.
>
> V2:
> - Addressed pr
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> .. because it would be a waste of time, so move the place where the
> check is done. Also, with this we won't risk printing "more than one
> pipe active, disabling compression" or "no output, disabling" when FBC
> is act
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> This may save a few picoseconds on !HAS_FBC platforms. And it also
> satisfies my OCD.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(
Reviewed-by: Rodrigo Vivi
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Since the mapping from CRTCs to planes is fixed, looking at the CRTC
> is essentially the same as looking at the plane. Also, the next
> patches wil start using the frontbuffer_bits macros, an
On Mon, Dec 8, 2014 at 8:53 AM, Daniel Vetter wrote:
> On Mon, Dec 08, 2014 at 02:09:15PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> We want to port FBC to the frontbuffer tracking infrastructure, but
>> for that we need to know what caused the object invalidation/flush so
>> we can r
wondering if this fixes: https://bugs.freedesktop.org/show_bug.cgi?id=87143
Reviewed-by: Rodrigo Vivi
On Mon, Dec 8, 2014 at 8:55 AM, Daniel Vetter wrote:
> On Mon, Dec 08, 2014 at 02:09:16PM -0200, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> We need this for FBC, and possibly for PSR too.
From: Paulo Zanoni
Kill the blt/render tracking we currently have and use the frontbuffer
tracking infrastructure.
Don't enable things by default yet.
v2: (Rodrigo) Fix small conflict on rebase and typo at subject.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo
just a note that I sent a reviwed v2: rebased and with typo fix.
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Kill the blt/render tracking we currently have and use the frontbuffer
> tracking infrastructure.
>
> Don't enable things by default yet.
>
> Signed-off-b
Reviewed-by: Rodrigo Vivi
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> I want to make this code a little more complicated, so let's extract
> the function first.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 46
> ++
I always ask myself if we should just clean the code and remove all
platforms before HSW that always had many fbc issues. So we could make
it simple and just do for pipe A for all platforms.
Anyway, this looks ok for now
Reviewed-by: Rodrigo Vivi
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wro
I keep my with to remove support for old gens but anyway:
Reviewed-by: Rodrigo Vivi
On Mon, Dec 8, 2014 at 8:09 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> So allow it.
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 6 --
> 1 file changed, 4 insertions(+)
On Mon, Dec 8, 2014 at 1:35 AM, Daniel Vetter wrote:
> On Fri, Dec 05, 2014 at 08:40:42PM -0500, Rodrigo Vivi wrote:
>> Since active function on VLV immediately activate PSR let's give more
>> time for idleness.
>>
>> v2: Rebase over intel_psr.c and fix typo.
>> v3: Revival: Manual tests indicated
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