Re: [Intel-gfx] [PATCH] drm/i915: Use BUILD_BUG if possible in the i915 WARN_ON

On Wed, 10 Dec 2014, Daniel Vetter wrote: > Faster feedback to errors is always better. This is inspired by the > addition to WARN_ONs to mask/enable helpers for registers to make sure > callers have the arguments ordered correctly: Pretty much always the > arguments are static. > > We use WARN_ON

[Intel-gfx] [PATCH 3/3] drm/i915: Disable PMSI sleep messages on all rings around context switches

There exists a current workaround to prevent a hang on context switch should the ring go to sleep in the middle of the restore, WaProgramMiArbOnOffAroundMiSetContext (applicable to all gen7+). In spite of disabling arbitration (which prevents the ring from powering down during the critical section)

[Intel-gfx] [PATCH 1/3] drm/i915: Invalidate media caches on gen7

In the gen7 pipe control there is an extra bit to flush the media caches, so let's set it during cache invalidation flushes. Cc: Simon Farnsworth Signed-off-by: Chris Wilson Cc: sta...@vger.kernel.org --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 1

[Intel-gfx] [PATCH 2/3] drm/i915: Force the CS stall for invalidate flushes

In order to act as a full command barrier by itself, we need to tell the pipecontrol to actually stall the command streamer while the flush runs. We require the full command barrier before operations like MI_SET_CONTEXT, which currently rely on a prior invalidate flush. References: https://bugs.fr

Re: [Intel-gfx] [PATCH] drm/i915/i9xx: check for panel on pipe before asserting panel unlock bits

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

[Intel-gfx] [PATCH 4/4] drm/i915: Skip gunit save/restore for cherryview

From: Deepak S With cherryview onwards, Gunit hardware itself save and restore all the Gunit registers. Skipping the "vlv_save_gunit_s0ix_state" & "vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/i915_drv.c | 7 +-- 1 file

[Intel-gfx] [PATCH 3/4] drm/i915: New offset for reading frequencies on CHV.

From: Deepak S Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run. Signed-off-by: Deepak S --- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu

[Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

From: Deepak S Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0 Based upon a patch from Jeff, but

[Intel-gfx] [PATCH 1/4] drm/i915/chv: Use timeout mode for RC6 on chv

From: Deepak S Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6. Signed-off-by: Deepak S Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/dr

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Rebalance runtime pm vs forcewake

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: From: Chris Wilson Calling intel_runtime_pm_put() is illegal from a soft-irq context, so revert the crude hack commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80c Author: Paulo Zanoni Date: Tue Apr 1 14:55:07 2014 -0300 drm/i915:

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Rebalance runtime pm vs forcewake

On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote: > > On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: > >From: Chris Wilson > > > >Calling intel_runtime_pm_put() is illegal from a soft-irq context, so > >revert the crude hack > > > >commit aa0b3b5bb8768c1a6a6788869d9c7015eae7e80

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Infrastructure for supporting different GGTT views per object

On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Things like reliable GGTT mappings and mirrored 2d-on-3d display will need to map objects into the same address space multiple times. Added a GGTT view concept and linked it with the VMA to distinguish between multiple instances

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Documentation for multiple GGTT views

On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote: From: Tvrtko Ursulin A short section describing background, implementation and intended usage. v2: * Align section name between template and DOC comment. (Michel Thierry) For: VIZ-4544 Signed-off-by: Tvrtko Ursulin Reviewed-by: Michel Thier

[Intel-gfx] [PATCH] drm/i915/bdw: Enable execlists by default where supported

Execlist support in the i915 driver is now considered good enough for the feature to be enabled by default on Gen8 and later and routinely tested. Adjusted i915 parameters structure initialization to reflect this and updated the comment in intel_sanitize_enable_execlists(). Issue: VIZ-2020 Signed-

Re: [Intel-gfx] [PATCH 1/8] drm/i915: Rebalance runtime pm vs forcewake

On Thursday 11 December 2014 03:45 PM, Chris Wilson wrote: On Fri, Dec 12, 2014 at 03:30:14PM +0530, Deepak S wrote: On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: From: Chris Wilson Calling intel_runtime_pm_put() is illegal from a soft-irq context, so revert the crude hack commi

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Assert that runtime pm is active on user fw access

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: From: Chris Wilson On user forcewake access, assert that runtime pm reference is held. Fix and cleanup the callsites accordingly. Signed-off-by: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_debugfs.c |

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Assert that runtime pm is active on user fw access

On Fri, Dec 12, 2014 at 05:09:26PM +0530, Deepak S wrote: > >@@ -564,17 +542,20 @@ void gen6_gt_force_wake_get(struct drm_i915_private > >*dev_priv, int fw_engine) > > intel_runtime_pm_get(dev_priv); > > I think we need to remove "intel_runtime_pm_get" here? > I see runtime_put is removed fro

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Skip uncore lock on earlier gens

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: From: Chris Wilson With gen < 6 we don't need to take uncore lock as we don't have anything to protect from concurrent access. v2: rebase and account for gen9 changes Signed-off-by: Chris Wilson (v1) Signed-off-by: Mika Kuoppala ---

Re: [Intel-gfx] [PATCH] drm/i915/bdw: Enable execlists by default where supported

On Thu, 11 Dec 2014, Thomas Daniel wrote: > Execlist support in the i915 driver is now considered good enough for the > feature to be enabled by default on Gen8 and later and routinely tested. > Adjusted i915 parameters structure initialization to reflect this and updated > the comment in intel_sa

Re: [Intel-gfx] [PATCH 2/8] drm/i915: Assert that runtime pm is active on user fw access

On Thursday 11 December 2014 05:23 PM, Chris Wilson wrote: On Fri, Dec 12, 2014 at 05:09:26PM +0530, Deepak S wrote: @@ -564,17 +542,20 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) intel_runtime_pm_get(dev_priv); I think we need to remove "intel_run

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Skip gunit save/restore for cherryview

On Fri, Dec 12, 2014 at 02:18:16PM +0530, deepa...@linux.intel.com wrote: > From: Deepak S > > With cherryview onwards, Gunit hardware itself save and restore all the > Gunit registers. Skipping the "vlv_save_gunit_s0ix_state" & > "vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.

[Intel-gfx] [PATCH] drm/i915: Use true PPGTT in Gen8 if execlists are enabled

When execlists submission is enabled, try full ppgtt by default. Note, this patch considers that execlist support has been enabled by default on Gen8. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git

Re: [Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

On Fri, 12 Dec 2014, deepa...@linux.intel.com wrote: > From: Deepak S > > Starting with Cherryview, devices may have a varying number of EU for > a given ID due to creative fusing. Punit support different frequency for > different fuse data. We use this patch to help get total eu enabled and > rea

Re: [Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

On Thursday 11 December 2014 05:39 PM, Jani Nikula wrote: On Fri, 12 Dec 2014, deepa...@linux.intel.com wrote: From: Deepak S Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Invalidate media caches on gen7

On Thu, Dec 11, 2014 at 08:16:59AM +, Chris Wilson wrote: > In the gen7 pipe control there is an extra bit to flush the media > caches, so let's set it during cache invalidation flushes. Bspec is telling me this bit is already present in snb, and calls it 'Generic Media State Clear'. Older Bsp

[Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

From: Sonika Jindal We were incorreectly bypassing the flush everytime which led to fifo underrun when more than one plane is enabled. Signed-off-by: Sonika Jindal --- drivers/gpu/drm/i915/intel_pm.c |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Disable PMSI sleep messages on all rings around context switches

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

[Intel-gfx] [PATCH v2] drm/i915/chv: Populate total EU count on Cherryview

From: Deepak S Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0 Based upon a patch from Jeff, but

[Intel-gfx] [PATCH 0/8] Resend of drm/i915: Keep drm_crtc->state in sync

I'm resending this series, now without the RFC status. Code is unchanged from the RFC. Ander Conselvan de Oliveira (8): drm/i915: Rename struct intel_crtc_config to intel_crtc_state drm/i915: Embedded struct drm_crtc_state in intel_crtc_state drm/i915: Pass new_config down do crtc_compute_cl

[Intel-gfx] [PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk()

So that we can get rid of the new_config pointer later. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 30 ++ 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 6/8] drm/i915: Remove intel_crtc->new_config pointer

There are no more users of that pointer since the new config is now passed down the call chain during mode set. Also, when the switch to atomic happens, the right config (state) should be derived from an atomic state structure. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/8] drm/i915: Rename struct intel_crtc_config to intel_crtc_state

The objective is to make this structure usable with the atomic helpers, so let's start with the rename. Patch generated with coccinelle: @@ @@ -struct intel_crtc_config +struct intel_crtc_state Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_drv.h | 4 +- driver

[Intel-gfx] [PATCH 4/8] drm/i915: Use local pipe_config varariable when available

In function that define a local pipe_config variable to point to crtc->config, replace remaining references to crtc->config with the local variable. This makes the code more consistent and easier to change in an automated manner. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 3/8] drm/i915: Pass new_config down do crtc_compute_clock

This reduces the number of direct users of crtc->new_config. At some point we'll be able to get rid of that pointer altogether, in favor of drm core state structs. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/intel_ddi.c

[Intel-gfx] [PATCH 2/8] drm/i915: Embedded struct drm_crtc_state in intel_crtc_state

And get rid of the duplicate mode structures. The bulk of the patch was generated with the following semantic patch. @@ struct intel_crtc_state *state; @@ -state->adjusted_mode +state->base.adjusted_mode @@ struct intel_crtc_state *state; @@ -state->requested_mode +state->base.mode @@ struct intel

[Intel-gfx] [PATCH 7/8] drm/i915: Make intel_crtc->config a pointer

To match the semantics of drm_crtc->state, which this will eventually become. @@ struct intel_crtc *crtc; @@ -&crtc->config +crtc->config @@ struct intel_crtc *crtc; identifier member; @@ -crtc->config.member +crtc->config->member @@ struct drm_crtc *crtc; @@ -&to_intel_crtc(crtc)->config +to_inte

[Intel-gfx] [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config

So that atomic operations will reference the right crtc state. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 462f22a..20b9

[Intel-gfx] [PATCH v2] drm/i915/bdw: Enable execlists by default where supported

Execlist support in the i915 driver is now considered good enough for the feature to be enabled by default on Gen8 and later and routinely tested. Adjusted i915 parameters structure initialization to reflect this and updated the comment in intel_sanitize_enable_execlists(). v2: Update the MODULE_P

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Keep drm_crtc->state in sync with intel_crtc->config

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

Re: [Intel-gfx] [PATCH 4/8] drm/i915: Reduce duplicated forcewake logic

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: From: Chris Wilson Introduce a structure to track the individual forcewake domains and use that to eliminate duplicate logic. v2: - Rebase on latest dinq (Mika) - for_each_fw_domain macro (Mika) - Handle reset atomically, kee

[Intel-gfx] lib: Fix out of tree build of version.h

Currently out of tree build fails because the version.h.tmp is generated into the source directory instead of the build directory where it is later looked for. This commit fixes it. From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Thu, 11 Dec 2014

[Intel-gfx] lib: Fix out of tree build of version.h

Currently out of tree build fails because the version.h.tmp is generated into the source directory instead of the build directory where it is later looked for. This commit fixes it. From 2c0617e21101d69e7219c6660936c0015f93f8ee Mon Sep 17 00:00:00 2001 From: Joonas Lahtinen Date: Thu, 11 Dec 2014

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Consolidate forcewake code

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: As we now have forcewake domains, take advantage of it by putting the differences in gen fw handling in data rather than in code. In past we have opencoded this quite extensively as the fw handling is in the fast path. There has also bee

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Make vlv and chv forcewake put generic.

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: These two were using a fw dance logic where posting read was done after both domain bit were set. When in other gens, the posting read is done immediately after setting the forcewake bit for each domain. Now bring these in line with othe

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Rename the forcewake get/put functions

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: We have multiple forcewake domains now on recent gens. Change the function naming to reflect this. v2: More verbose names (Chris) Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_debugfs.c | 8 drivers/gpu/dr

[Intel-gfx] [PATCH 1/5] drm/i915/opregion: use BUILD_BUG_ON to verify mailbox struct sizes

Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_opregion.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index d8de1d5140a7..bce9bbe05549 100644 --- a/drivers/gpu/drm/i915/intel_opregion.c +++ b/dr

[Intel-gfx] [PATCH 0/5] drm/i915/opregion updates

Hi all, here's a few updates to opregion. Patches 1-4 should be pretty trivial and not do anything drastic. Patch 5 starts using the extended DIDL, but I doubt it will make a huge difference anyway. It might prove to be useful prep stuff for adding more sense to our CADL handling. BR, Jani. Jani

[Intel-gfx] [PATCH 2/5] drm/i915/opregion: add new opregion stuff

Inluding extended didl and cpdl fields Present since opregion version 3.0. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_opregion.c | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/inte

[Intel-gfx] [PATCH 5/5] drm/i915/opregion: start using extended didl

Adding support for did2, or the extended support display devices ID list, increases the total to 15. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_opregion.c | 28 +--- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_o

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Follow the forcewake domains type on hw accessors

On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: Forcewake domain code uses unsigned int as a type for 'domains mask'. Bring the hw accessors inline with this. Suggested-by: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm

[Intel-gfx] [PATCH 3/5] drm/i915/opregion: prefer DRM logging functions over pr_warn and dev_dbg

Conform to same style as the rest of the driver. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_opregion.c | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c index 10c60199029d..

[Intel-gfx] [PATCH 4/5] drm/i915/opregion: abstract didl and did2 getter and setter

Make it easier to handle the extended didl. No functional changes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_opregion.c | 50 +++ 1 file changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/d

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Enum forcewake domains and domain identifiers

On Tuesday 09 December 2014 05:16 PM, Mika Kuoppala wrote: Make the domains and domain identifiers enums. To emphasize the difference in order to avoid mistakes. Suggested-by: Daniel Vetter Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.h | 41 +--

Re: [Intel-gfx] [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable

> -Original Message- > From: Nguyen, Michael H > Sent: Monday, December 08, 2014 10:34 PM > To: intel-gfx@lists.freedesktop.org > Cc: Bloomfield, Jon; Brad Volkin > Subject: [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable > > From: Brad Volkin > > By adding a new exec_ent

Re: [Intel-gfx] [PATCH] drm/i915: save/restore GMBUS freq across suspend/resume on gen4

On Wed, 10 Dec 2014, Jesse Barnes wrote: > On Wed, 10 Dec 2014 22:35:37 +0200 > Ville Syrjälä wrote: > >> On Wed, Dec 10, 2014 at 12:16:05PM -0800, Jesse Barnes wrote: >> > Should probably just init this in the GMbus code all the time, >> > based on the cdclk and HPLL like we do on newer platform

[Intel-gfx] [PULL] drm-intel-next-fixes

Hi Dave - Here's a batch of i915 fixes for 3.19. BR, Jani. The following changes since commit 00f0b3781028605910cb4662a0f8a4849b445fc2: drm/i915: Reject modeset when the same digital port is used more than once (2014-12-03 09:31:53 +0100) are available in the git repository at: git://an

Re: [Intel-gfx] [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code

> -Original Message- > From: Nguyen, Michael H > Sent: Monday, December 08, 2014 10:34 PM > To: intel-gfx@lists.freedesktop.org > Cc: Bloomfield, Jon; Brad Volkin > Subject: [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code > > From: Brad Volkin > > Move it to a separate

Re: [Intel-gfx] [PATCH] drm/i915: vlv: fix IRQ masking when uninstalling interrupts

On Wed, 10 Dec 2014, Ville Syrjälä wrote: > On Thu, Nov 20, 2014 at 04:05:55PM +0200, Imre Deak wrote: >> irq_mask should include all IRQ bits that we want to mask, but atm we >> set it incorrectly to the inverse of this. If the mask is used >> subsequently to enable/disable some IRQ bits, we may

Re: [Intel-gfx] lib: Fix out of tree build of version.h

This e-mail can be disregarded. It contains no secrets no nothing, simply sent from wrong address. On to, 2014-12-11 at 13:11 +, Lahtinen, Joonas wrote: > Currently out of tree build fails because the version.h.tmp is generated > into the source directory instead of the build directory where i

[Intel-gfx] [PATCH 1/7] drm/plane-helper: Test for plane disable earlier

drm_plane_helper_check_update() currently uses crtc before testing whether we're disabling the plane (fb == NULL). Move the fb test before the first crtc usage so that crtc == NULL doesn't have to be handled by the caller. Signed-off-by: Matt Roper --- drivers/gpu/drm/drm_plane_helper.c | 16 ++

Re: [Intel-gfx] [PATCH] drm/i915/i9xx: check for panel on pipe before asserting panel unlock bits

On 11 Dec 2014 00:40:28 -0800 shuang...@intel.com wrote: > Tested-By: PRC QA PRTS (Patch Regression Test System Contact: > shuang...@intel.com) > -Summary- > Platform Delta drm-intel-nightly Series

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

On 12/11/2014 12:28 PM, sonika.jin...@intel.com wrote: From: Sonika Jindal We were incorreectly bypassing the flush everytime which led to fifo underrun when more than one plane is enabled. Signed-off-by: Sonika Jindal --- drivers/gpu/drm/i915/intel_pm.c |3 +-- 1 file changed, 1 inse

[Intel-gfx] [RFC] drm/i915: Reduce locking in command submission

From: Tvrtko Ursulin Eliminate six needless spin lock/unlock pairs when writing ELSP. RFC for now with some #define copy and paste. Signed-off-by: Tvrtko Ursulin Cc: Dave Gordon --- drivers/gpu/drm/i915/intel_lrc.c | 16 +--- 1 file changed, 9 insertions(+), 7 deletions(-) diff

Re: [Intel-gfx] [PATCH 1/7] drm/plane-helper: Test for plane disable earlier

On Thu, Dec 11, 2014 at 07:20:57AM -0800, Matt Roper wrote: > drm_plane_helper_check_update() currently uses crtc before testing whether > we're disabling the plane (fb == NULL). Move the fb test before the first > crtc > usage so that crtc == NULL doesn't have to be handled by the caller. > > S

Re: [Intel-gfx] [PATCH v3 0/8] Add enlightenments for vGPU

Hi, I'll try to do the detailed review of your series in the following few days. I might ask some questions on the design also to help me understand the bigger picture. First thing, I see that patches are checkpatch.pl clean, apart when run in strict mode. I think Daniel prefers "--strict"

Re: [Intel-gfx] [PATCH v3 1/8] drm/i915: Introduce a PV INFO page structure for Intel GVT-g.

On 11/13/2014 12:02 PM, Yu Zhang wrote: Introduce a PV INFO structure, to facilitate the Intel GVT-g technology, which is a GPU virtualization solution with mediated pass-through. This page contains the shared information between i915 driver and the host emulator. For now, this structure utilize

Re: [Intel-gfx] [PATCH] drm/i915: Use true PPGTT in Gen8 if execlists are enabled

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

Re: [Intel-gfx] [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable

On 12/11/2014 05:26 AM, Bloomfield, Jon wrote: -Original Message- From: Nguyen, Michael H Sent: Monday, December 08, 2014 10:34 PM To: intel-gfx@lists.freedesktop.org Cc: Bloomfield, Jon; Brad Volkin Subject: [PATCH v6 4/5] drm/i915: Mark shadow batch buffers as purgeable From: Brad Vo

Re: [Intel-gfx] [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code

On 12/11/2014 05:49 AM, Bloomfield, Jon wrote: -Original Message- From: Nguyen, Michael H Sent: Monday, December 08, 2014 10:34 PM To: intel-gfx@lists.freedesktop.org Cc: Bloomfield, Jon; Brad Volkin Subject: [PATCH v6 5/5] drm/i915: Tidy up execbuffer command parsing code From: Bra

Re: [Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

[Intel-gfx] [PATCH v7 4/5] drm/i915: Mark shadow batch buffers as purgeable

From: Brad Volkin By adding a new exec_entry flag, we cleanly mark the shadow objects as purgeable after they are on the active list. v2: - Move 'shadow_batch_obj->madv = I915_MADV_WILLNEED' inside _get fnc (danvet, from v4 6/7 feedback) v3: - Remove duplicate 'madv = I915_MADV_WILLNEED' (dan

[Intel-gfx] [PATCH v7 3/5] drm/i915: Use batch length instead of object size in command parser

From: Brad Volkin Previously we couldn't trust the user-supplied batch length because it came directly from userspace (i.e. untrusted code). It would have affected what commands software parsed without regard to what hardware would actually execute, leaving a potential hole. With the parser now

[Intel-gfx] [PATCH v7 1/5] drm/i915: Implement a framework for batch buffer pools

From: Brad Volkin This adds a small module for managing a pool of batch buffers. The only current use case is for the command parser, as described in the kerneldoc in the patch. The code is simple, but separating it out makes it easier to change the underlying algorithms and to extend to future u

[Intel-gfx] [PATCH v7 5/5] drm/i915: Tidy up execbuffer command parsing code

From: Brad Volkin Move it to a separate function since the main do_execbuffer function already has so much going on. v2: - Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7 feedback) Issue: VIZ-4719 Signed-off-by: Brad Volkin --- drivers/gpu/drm/i915/i915_cmd_parser.c | 8

[Intel-gfx] [PATCH v7 0/5] Command parser batch buffer copy

From: "Michael H. Nguyen" This is v7 in response to http://lists.freedesktop.org/archives/intel-gfx/2014-December/057033.html Minor updates from the last rev - Keep batch pool in LRU order (Daniel) - Remove duplicate madv assignments (Daniel) Brad Volkin (5): drm/i915: Implement a framework

[Intel-gfx] [PATCH v7 2/5] drm/i915: Use batch pools with the command parser

From: Brad Volkin This patch sets up all of the tracking and copying necessary to use batch pools with the command parser and dispatches the copied (shadow) batch to the hardware. After this patch, the parser is in 'enabling' mode. Note that performance takes a hit from the copy in some cases a

[Intel-gfx] [PATCH] drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist

This will allow us to read the number of dispatched compute threads for GL_ARB_pipeline_statistics_query. Signed-off-by: Jordan Justen Cc: Ben Widawsky --- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 +++- drivers/gpu/drm/i915/i915_reg.h| 23 --- 2 files changed, 15

Re: [Intel-gfx] [PATCH v2] drm/i915/bdw: Enable execlists by default where supported

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

Re: [Intel-gfx] [PATCH 5/5] drm/i915/opregion: start using extended didl

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform Delta drm-intel-nightly Series Applied PNV 364/364

Re: [Intel-gfx] [PATCH] drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist

On Thu, Dec 11, 2014 at 01:28:09PM -0800, Jordan Justen wrote: > This will allow us to read the number of dispatched compute threads > for GL_ARB_pipeline_statistics_query. > > Signed-off-by: Jordan Justen > Cc: Ben Widawsky Reviewed-by: Ben Widawsky [snip] __

[Intel-gfx] [PATCH] drm/i915: Refactor work that can sleep out of commit (v4)

Once we integrate our work into the atomic pipeline, plane commit operations will need to happen with interrupts disabled, due to vblank evasion. Our commit functions today include sleepable work, so those operations need to be split out and run either before or after the atomic register programmi

[Intel-gfx] [PATCH] drm/i915: Prepare for atomic plane helpers (v7)

Add the new driver entrypoints that will be called by the atomic plane helpers. This patch does not actually switch over to the new plane helpers yet, so there should be no functional change here. Also note that although plane programming was already split into check/prepare/commit steps, some of

[Intel-gfx] [PATCH v2] drm/i915/chv: Use timeout mode for RC6 on chv

From: Deepak S Higher RC6 residency is observed using timeout mode instead of EI mode. It's Recommended to use TO Method for RC6. v2: Add comment about timeout threshold. (Tom) Signed-off-by: Deepak S Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 5 +++-- 1 file changed,

[Intel-gfx] [QA 12/12 ww50] Testing report for `drm-intel-testing` (was: Updated -next)

Summary We covered the platform: Braswell, Broadwell, Baytrail, Haswell, Ivybridge, Ironlake In this circle, 3 new bugs are filed: 87253 [BSW drm-intel-fixes]Display is blank after system boots 87223

Re: [Intel-gfx] [PATCH] drm/i915: Changes required to enable DSI Video Mode on CHT

On 12/10/2014 7:38 PM, Gaurav K Singh wrote: For CHT changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel