v2: Fix the 3rd plane/cursor logic (Pradeep Bhat)
v3: Fix one-by-one error in the DDB allocation code
v4: Rebase on top of the skl_pipe_pixel_rate() argument change
v5: Replace the available/start/end output parameters of
skl_ddb_get_pipe_allocation_limits() by a single ddb entry constify
a
On Fri, Sep 19, 2014 at 01:03:15PM +0300, Ville Syrjälä wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 0ddcbad..756ff16 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3393,6 +3393,15 @@ sta
On 26 September 2014 08:25, Jani Nikula wrote:
> On Wed, 24 Sep 2014, Mathias Burén wrote:
>> I've a 1440p display with a non-sufficient/corrupt EDID.
>
> Just to double check, you mean the display really is broken in this
> regard, *not* that the driver is unable to read the EDID?
I think the E
On 27 September 2014 16:39, Mathias Burén wrote:
> On 26 September 2014 08:25, Jani Nikula wrote:
>> On Wed, 24 Sep 2014, Mathias Burén wrote:
>>> I've a 1440p display with a non-sufficient/corrupt EDID.
>>
>> Just to double check, you mean the display really is broken in this
>> regard, *not* t
