Re: [Intel-gfx] [PATCH 0/4] module: add support for unsafe, tainting parameters

On Wed, 20 Aug 2014, Rusty Russell wrote: > I've applied this cleanup on top, however. > > Cheers, > Rusty. > > Subject: param: check for tainting before calling set op. > > This means every set op doesn't need to call it, and it can move into > params.c. Much better, thanks. I was looking for a

Re: [Intel-gfx] [PATCH] drm/i915: don't warn if backlight unexpectedly enabled

On Tue, 19 Aug 2014, Daniel Vetter wrote: On Tue, Aug 19, 2014 at 4:07 AM, Scot Doyle wrote: BIOS or firmware can modify hardware state during suspend/resume, for example on the Toshiba CB35 or Lenovo T400, so log a debug message instead of a warning if the backlight is unexpectedly enabled.

Re: [Intel-gfx] Responsiveness Changes to i915 Driver

On Wed, 20 Aug 2014, "Wilde, Martin" wrote: > Hi Jani - the DRM_DEBUG_KMS is part of the DRM_DEBUG_CODE preprocessor > macro and thus not available unavailable in a non-debug build kernel from > my understanding. > > The issue we have seen many times is that the BIOS (firmware) team does > not set

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave - Display fixes from Ville and Imre, all cc: stable. BR, Jani. The following changes since commit 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9: Linux 3.17-rc1 (2014-08-16 10:40:26 -0600) are available in the git repository at: git://anongit.freedesktop.org/drm-intel tags/drm-intel-f

Re: [Intel-gfx] [PATCH v2] drm/i915: Fix to Enable GT/PM Interrupts for cherryview.

On Fri, Aug 22, 2014 at 08:32:40AM +0530, deepa...@linux.intel.com wrote: > From: Deepak S > > Programing GT IER interrupts was fumbled while enabling Interrupts for > gen8 > > This is a regression from > commit abd58f0175915bed644aa67c8f69dc571b8280e0 > Author: Ben Widawsky > Date:

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add 180 degree primary plane rotation support

On Thu, Aug 21, 2014 at 11:45:41AM +0530, sonika.jin...@intel.com wrote: > From: Sonika Jindal > > Primary planes support 180 degree rotation. Expose the feature > through rotation drm property. > > v2: Calculating linear/tiled offsets based on pipe source width and > height. Added 180 degree ro

[Intel-gfx] [PATCH] drm/i915/bdw: Render state init for Execlists

From: Oscar Mateo The batchbuffer that sets the render context state is submitted in a different way, and from different places. We needed to make both the render state preparation and free functions outside accesible, and namespace accordingly. This mess is so that all LR, LRC and Execlists fun

Re: [Intel-gfx] [PATCH 35/43] drm/i915/bdw: Make sure error capture keeps working with Execlists

> -Original Message- > From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel > Vetter > Sent: Friday, August 15, 2014 1:14 PM > To: Daniel, Thomas > Cc: intel-gfx@lists.freedesktop.org; Mika Kuoppala > Subject: Re: [Intel-gfx] [PATCH 35/43] drm/i915/bdw: Make sure error

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add 180 degree primary plane rotation support

On 8/21/2014 2:03 PM, Ville Syrjälä wrote: On Thu, Aug 21, 2014 at 11:45:41AM +0530, sonika.jin...@intel.com wrote: From: Sonika Jindal Primary planes support 180 degree rotation. Expose the feature through rotation drm property. v2: Calculating linear/tiled offsets based on pipe source wid

[Intel-gfx] [PATCH 2/2] drm/i915: improve assert_panel_unlocked

Fix assert_panel_unlocked for vlv/chv, and improve it a bit for non-LVDS. Also don't pretend it works for DDI. There's still work to do to get this right for eDP on PCH platforms, but this is a start. Signed-off-by: Jani Nikula --- So I wanted to quickly fix assert_panel_unlocked, but for such

[Intel-gfx] [PATCH 1/2] drm/i915: fix panel unlock register mask

Use the correct mask for the unlock bits. In theory this could have lead to incorrect asserts but this is unlikely in practise. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_displ

Re: [Intel-gfx] [PATCH v3] drm/i915: Rework GPU reset sequence to match driver load & thaw

Hi Daniel, Is there anything else needing done before this patch can be merged? Thanks, Alistair. > -Original Message- > From: Mika Kuoppala [mailto:mika.kuopp...@linux.intel.com] > Sent: Tuesday, August 19, 2014 1:36 PM > To: Mcaulay, Alistair; intel-gfx@lists.freedesktop.org > Subject:

Re: [Intel-gfx] [PATCH 1/2] drm/i915: fix panel unlock register mask

2014-08-21 9:06 GMT-03:00 Jani Nikula : > Use the correct mask for the unlock bits. In theory this could have lead > to incorrect asserts but this is unlikely in practise. > > Signed-off-by: Jani Nikula Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file cha

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add 180 degree primary plane rotation support

On Thu, Aug 21, 2014 at 05:14:35PM +0530, Jindal, Sonika wrote: > > > On 8/21/2014 2:03 PM, Ville Syrjälä wrote: > > On Thu, Aug 21, 2014 at 11:45:41AM +0530, sonika.jin...@intel.com wrote: > >> From: Sonika Jindal > >> > >> Primary planes support 180 degree rotation. Expose the feature > >> thr

Re: [Intel-gfx] [PATCH 1/2] drm/i915: fix panel unlock register mask

On Thu, Aug 21, 2014 at 03:06:25PM +0300, Jani Nikula wrote: > Use the correct mask for the unlock bits. In theory this could have lead > to incorrect asserts but this is unlikely in practise. > > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_display

[Intel-gfx] [PATCH 02/16] kms_cursor_crc: Use I915_TILING_NONE to create fbs

Signed-off-by: Damien Lespiau --- tests/kms_cursor_crc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 6af30fd..47531f3 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -235,7 +235,7 @@ static boo

[Intel-gfx] [PATCH 05/16] kms_flip: Adjust to the new igt_create_fb*() API

Signed-off-by: Damien Lespiau --- tests/kms_flip.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/kms_flip.c b/tests/kms_flip.c index 5cd8c2f..0faed85 100644 --- a/tests/kms_flip.c +++ b/tests/kms_flip.c @@ -227,7 +227,7 @@ static void emit_fence_stress(s

[Intel-gfx] [PATCH 04/16] kms_fence_pin_leak: Use I915_TILING_X to create fbs

Signed-off-by: Damien Lespiau --- tests/kms_fence_pin_leak.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c index 51bc72f..93f4e16 100644 --- a/tests/kms_fence_pin_leak.c +++ b/tests/kms_fence_pin_leak.c @@ -127,12 +

[Intel-gfx] [PATCH 07/16] kms_mmio_vs_cs_flip: Adjust to the new igt_create_.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_mmio_vs_cs_flip.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/kms_mmio_vs_cs_flip.c b/tests/kms_mmio_vs_cs_flip.c index 243e424..09396a9 100644 --- a/tests/kms_mmio_vs_cs_flip.c +++ b/tests/kms_mmio_vs_cs_flip.

[Intel-gfx] [PATCH 03/16] kms_fbc_crc: Use I915_TILING_X to create fbs

Signed-off-by: Damien Lespiau --- tests/kms_fbc_crc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_fbc_crc.c b/tests/kms_fbc_crc.c index 9aeffd0..5ab048f 100644 --- a/tests/kms_fbc_crc.c +++ b/tests/kms_fbc_crc.c @@ -307,12 +307,12 @@ static bool prepare_test(

[Intel-gfx] [PATCH 12/16] kms_setmode: Adjust to the igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_setmode.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c index 59e2434..a43af1c 100644 --- a/tests/kms_setmode.c +++ b/tests/kms_setmode.c @@ -179,16 +179,14 @@ static void create_fb_for_

[Intel-gfx] [PATCH 06/16] kms_flip_tiling: Adjust to the new igt_create_.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_flip_tiling.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/kms_flip_tiling.c b/tests/kms_flip_tiling.c index 6f8ee94..1f2caac 100644 --- a/tests/kms_flip_tiling.c +++ b/tests/kms_flip_tiling.c @@ -81,7 +81,7 @@ test_fli

[Intel-gfx] [PATCH i-g-t 00/16] Use a tiling format in fb creation functions

We've been assuming that X-tiled was the only format we are able to scan out, this will change in a near future, so this series prepares i-g-t for that. -- Damien Damien Lespiau (16): lib: Change the fb creation functions to take fully qualified tiling formats kms_cursor_crc: Use I915_TI

[Intel-gfx] [PATCH 08/16] kms_pipe_crc_basic: Adjust to the new igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_pipe_crc_basic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_pipe_crc_basic.c b/tests/kms_pipe_crc_basic.c index 15aba2f..510a7d5 100644 --- a/tests/kms_pipe_crc_basic.c +++ b/tests/kms_pipe_crc_basic.c @@ -138,7 +138,7

[Intel-gfx] [PATCH 13/16] kms_sink_crc_basic: Adjust to the new igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_sink_crc_basic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_sink_crc_basic.c b/tests/kms_sink_crc_basic.c index b977dec..443f82e 100644 --- a/tests/kms_sink_crc_basic.c +++ b/tests/kms_sink_crc_basic.c @@ -70,7 +70,7 @

[Intel-gfx] [PATCH 10/16] kms_psr_sink_crc: Adjust to the new igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_psr_sink_crc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c index 8e8c908..909d6ca 100644 --- a/tests/kms_psr_sink_crc.c +++ b/tests/kms_psr_sink_crc.c @@ -108,7 +108,7 @

[Intel-gfx] [PATCH 11/16] kms_render: Adjust to the new igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_render.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/kms_render.c b/tests/kms_render.c index f457929..db2ed45 100644 --- a/tests/kms_render.c +++ b/tests/kms_render.c @@ -125,10 +125,12 @@ static int test_format(const

[Intel-gfx] [PATCH 01/16] lib: Change the fb creation functions to take fully qualified tiling formats

In the future, we'll need more than X tiling here. So give a full enum instead of bool meaning X-tiled. It's fine to do this change without updating the users just yet as 'true' happens to be I915_TILING_X. Signed-off-by: Damien Lespiau --- lib/igt_fb.c | 37 +++-

[Intel-gfx] [PATCH 14/16] pm_lpsp: Adjust to the new igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/pm_lpsp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/pm_lpsp.c b/tests/pm_lpsp.c index 250b140..78d6d08 100644 --- a/tests/pm_lpsp.c +++ b/tests/pm_lpsp.c @@ -84,9 +84,8 @@ static uint32_t create_fb(int drm_fd, int width,

[Intel-gfx] [PATCH 15/16] pm_rpm: Adjust to the new igt_create*fb() API

Signed-off-by: Damien Lespiau --- tests/pm_rpm.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c index 841566b..b691ae3 100644 --- a/tests/pm_rpm.c +++ b/tests/pm_rpm.c @@ -285,7 +285,7 @@ static bool init_modeset_params_f

[Intel-gfx] [PATCH 09/16] kms_plane: Adjust to the new igt_create.*fb() API

Signed-off-by: Damien Lespiau --- tests/kms_plane.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/kms_plane.c b/tests/kms_plane.c index 42af2fb..07b1637 100644 --- a/tests/kms_plane.c +++ b/tests/kms_plane.c @@ -78,7 +78,7 @@ test_grab_crc(data_t *data, igt_out

[Intel-gfx] [PATCH 16/16] testdisplay: Make the desired tiling mode an unsigned int

We may be able to scan out more tiling formats in the future. Signed-off-by: Damien Lespiau --- tests/testdisplay.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tests/testdisplay.c b/tests/testdisplay.c index 89ee110..dbca203 100644 --- a/tests/testdisplay.c

[Intel-gfx] [PATCH i-g-t] lib/fb: Assert, instead of silently failing, when creating fbs

We were either returning 0, or a negative value cast to an unsigned int for errors and the clients of that API weren't exactly checking anything. We're in luck, we can take shortcuts in a testing library to just assert when an expected error occurs. Signed-off-by: Damien Lespiau --- lib/igt_fb.

[Intel-gfx] [PATCH i-g-t] lib/fb: Replace straight igt_fail() by asserts with debug messages

Signed-off-by: Damien Lespiau --- lib/igt_fb.c | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 30b8593..f383970 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -516,7 +516,8 @@ static cairo_format_t drm_format_to_cairo(uint32_t drm

Re: [Intel-gfx] [PATCH 2/2] drm/i915: improve assert_panel_unlocked

On Thu, Aug 21, 2014 at 03:06:26PM +0300, Jani Nikula wrote: > Fix assert_panel_unlocked for vlv/chv, and improve it a bit for > non-LVDS. Also don't pretend it works for DDI. There's still work to do > to get this right for eDP on PCH platforms, but this is a start. > > Signed-off-by: Jani Nikula

Re: [Intel-gfx] [PATCH 2/2] drm/i915: improve assert_panel_unlocked

2014-08-21 11:56 GMT-03:00 Ville Syrjälä : > On Thu, Aug 21, 2014 at 03:06:26PM +0300, Jani Nikula wrote: >> Fix assert_panel_unlocked for vlv/chv, and improve it a bit for >> non-LVDS. Also don't pretend it works for DDI. There's still work to do >> to get this right for eDP on PCH platforms, but

[Intel-gfx] [PATCH] drm/i915: Ignore VBT backlight presence check on Acer C720 (4005U)

commit c675949ec58ca50d5a3ae3c757892f1560f6e896 drm/i915: do not setup backlight if not available according to VBT prevents backlight setup on the Acer C720 (Core i3 4005U CPU), which has a misconfigured VBT. Apply quirk to ignore the VBT backlight presence check during backlight setup. Signe

Re: [Intel-gfx] [PATCH] drm/i915: FBC flush nuke for BDW

List was accidentally drop. I didn't mean it. Sorry. And yes, you are right, we need a way to reduce nukes and cleans similar that we have for psr. I'll try it. On Tue, Aug 19, 2014 at 11:58 AM, Daniel Vetter wrote: > Readding intel-gfx. Please don't drop mailing lists cc's without telling > m

Re: [Intel-gfx] [PATCH] drm/i915/dp: Backlight PWM enable before BL Enable assert

On 08/20/2014 04:23 AM, Ville Syrjälä wrote: On Mon, Aug 18, 2014 at 01:48:35PM -0700, clinton.a.tay...@intel.com wrote: From: Clint Taylor Backlight on delay uses PWM enable time to seperate PWM to backlight enable assert. Previous time difference used timing from VDD enable which occur sever

[Intel-gfx] [PATCH 2/3] drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating

From: Paulo Zanoni Because CHV uses cherryview_init_clock_gating instead of gen8_init_clock_gating. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) I really wish we were using the three-letter-acronyms instead of the fu

[Intel-gfx] [PATCH 1/3] drm/i915: call lpt_init_clock_gating on BDW too

From: Paulo Zanoni Because BDW has WPT, which is equivalent to LPT. This is just like the CPT/PPT case. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index

[Intel-gfx] [PATCH 3/3] drm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspend

From: Paulo Zanoni On BDW we're seeing a problem that after we runtime resume, the outputs connected to DDI C are not detected: they don't appear in the SDEISR register and GMBUS transactions don't work. They stop working at the moment we call intel_opregion_notify_adapter() during runtime suspen

Re: [Intel-gfx] [PATCH 1/3] drm/i915: call lpt_init_clock_gating on BDW too

On Thu, Aug 21, 2014 at 05:09:36PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because BDW has WPT, which is equivalent to LPT. This is just like the > CPT/PPT case. > > Signed-off-by: Paulo Zanoni Maybe we should mention that Satheesh suggested the change with a: Suggested-by: Sathees

Re: [Intel-gfx] [REGRESSION BISECTED] backlight control stops workin with 3.14 and later

On 19-8-2014 3:29, Jani Nikula wrote: > On Tue, 19 Aug 2014, Bertrik Sikken wrote: >>> On Sun, 17 Aug 2014, Bertrik Sikken wrote: On 15-8-2014 3:43, Jani Nikula wrote: > On Thu, 14 Aug 2014, Bertrik Sikken wrote: >> Attached is dmesg output from booting kernel 3.14-2 (debian un

Re: [Intel-gfx] [PATCH 2/3] drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gating

On Thu, Aug 21, 2014 at 05:09:37PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because CHV uses cherryview_init_clock_gating instead of > gen8_init_clock_gating. > > Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau -- Damien > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++--

Re: [Intel-gfx] [PATCH 3/3] drm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspend

On Thu, Aug 21, 2014 at 05:09:38PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > On BDW we're seeing a problem that after we runtime resume, the > outputs connected to DDI C are not detected: they don't appear in the > SDEISR register and GMBUS transactions don't work. They stop working > a

Re: [Intel-gfx] [PATCH 1/3] drm/i915: call lpt_init_clock_gating on BDW too

On Thu, Aug 21, 2014 at 05:09:36PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because BDW has WPT, which is equivalent to LPT. This is just like the > CPT/PPT case. > > Signed-off-by: Paulo Zanoni It'd be probably good to have drm/i915/bdw: in the subject to ease back porting for prod

[Intel-gfx] [PATCH 00/68] Broadwell 48b addressing and prelocations (no relocs)

The primary goal of these patches is to introduce what I've started calling, "prelocations" on Broadwell. A prelocation is like a relocation, except not. When a GPU client specifies a prelocation, it is instructing the kernel where in the GPU address the buffer should be mapped. The mechanic works

[Intel-gfx] [PATCH 07/68] drm/i915/error: Do a better job of disambiguating VMAs

Some of the original PPGTT patches in this area where unmerged, and this left a lot of confusion in our error capture with regard to which vm/obj we want to capture. There have been at least a couple of patches from Chris, and myself to try to fix this up; so here is another shot. Nobody running wi

[Intel-gfx] [PATCH 06/68] drm/i915/error: vma error capture prettyify

Rename some variables, and clean up the code a bit to make things clearer in our error capture. There isn't an intentional functional change here. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gpu_error.c | 55 --- 1 file changed, 32 insertions(+), 23

[Intel-gfx] [PATCH 03/68] drm/i915/ppgtt: Load address space after mi_set_context

The simple explanation is, the docs say to do this for GEN8. Perhaps we want to do this for GEN7 too, I am not certain. PDPs are saved and restored with context. Contexts (without execlists) only exist on the render ring. The docs say that PDPs are not power context save/restored. I've learned th

[Intel-gfx] [PATCH 08/68] drm/i915/error: Capture vmas instead of BOs

To follow up on the last patch, we can now capture the VMAs instead of the BOs. The hope if we get more accurate error capture while debugging PPGTT. Note that this does not impact the previous argument about whether to capture all VMAs, or just the guilty VMA. This merely allows the code to do wh

[Intel-gfx] [PATCH 09/68] drm/i915: Add some extra guards in evict_vm

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_evict.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c index bbf4b12..38297d3 100644 --- a/drivers/gpu/drm/i915/i915_gem_evict.c

[Intel-gfx] [PATCH 05/68] drm/i915/ctx: Return earlier on failure

As what was correctly debugged here: commit acc240d41ea1ab9c488a79219fb313b5b46265ae Author: Daniel Vetter Date: Thu Dec 5 15:42:34 2013 +0100 drm/i915: Fix use-after-free in do_switch It then becomes apparent that the default context cannot be the context being switched to for context swi

[Intel-gfx] [PATCH 01/68] drm/i915: Split up do_switch

There are two important reasons for this patch. It should make the existing code a lot more readable. It also makes the next patch much easier to understand in my opinion. There are 2 main variables that effect this function, leaving 4 permutations: ring: RCS vs !RCS PPGTT: full or not I didn't fi

[Intel-gfx] [PATCH 11/68] drm/i915: More correct (slower) ppgtt cleanup

If a VM still have objects which are bound (exactly: have a node reserved in the drm_mm), and we are in the middle of a reset, we have no hope of the standard methods fixing the situation (ring idle won't work). We must therefore let the reset handler take it's course, and then we can resume tearin

[Intel-gfx] [PATCH 10/68] drm/i915: Make an uninterruptible evict

There are no users of this yet, but the idea is presented and split out to find bugs. Also, while here, return -ERESTARTSYS to the caller, in case they want to do something with it. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h| 2 +- drivers/gpu/drm/i915/i915_gem

[Intel-gfx] [PATCH 12/68] drm/i915: Defer PPGTT cleanup

The last patch made PPGTT free cases correct. It left a major problem though where in many cases it was possible to have to idle the GPU in order to destroy a VM. This is really unfortunate as it is stalling the active GPU process for the dying GPU process. The workqueue grew very tricky. I left i

[Intel-gfx] [PATCH 02/68] drm/i915: Extract l3 remapping out of ctx switch

This is just a cosmetic change to try to put do_switch_rcs on a diet. As it stands, the function was quite complex, and error prone. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_context.c | 32 1 file changed, 20 insertions(+), 12 deletions(-) d

[Intel-gfx] [PATCH 04/68] drm/i915: Fix another another use-after-free in do_switch

See the following for many more details. commit acc240d41ea1ab9c488a79219fb313b5b46265ae Author: Daniel Vetter Date: Thu Dec 5 15:42:34 2013 +0100 drm/i915: Fix use-after-free in do_switch In this case, the issue is only for full PPGTT: do_switch context_unref ppgtt_release i9

[Intel-gfx] [PATCH 27/68] drm/i915: Setup less PPGTT on failed pagedir

The current code will both potentially print a WARN, and setup part of the PPGTT structure. Neither of these harm the current code, it is simply for clarity, and to perhaps prevent later bugs, or weird debug messages. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 -

[Intel-gfx] [PATCH 55/68] drm/i915/bdw: Make pdp allocation more dynamic

This transitional patch doesn't do much for the existing code. However, it should make upcoming patches to use the full 48b address space a bit easier to swallow. The patch also introduces the PML4, ie. the new top level structure of the page tables. Signed-off-by: Ben Widawsky --- drivers/gpu/d

[Intel-gfx] [PATCH 28/68] drm/i915: clean up PPGTT init error path

The old code (I'm having trouble finding the commit) had a reason for doing things when there was an error, and would continue on, thus the !ret. For the newer code however, this looks completely silly. Follow the normal idiom of if (ret) return ret. Also, put the pde wiring in the gen specific i

[Intel-gfx] [PATCH 36/68] drm/i915: Generalize GEN6 mapping

Having a more general way of doing mappings will allow the ability to easy map and unmap a specific page table. Specifically in this case, we pass down the page directory + entry, and the page table to map. This works similarly to the x86 code. The same work will need to happen for GEN8. At that p

[Intel-gfx] [PATCH 37/68] drm/i915: Clean up pagetable DMA map & unmap

Map and unmap are common operations across all generations for pagetables. With a simple helper, we can get a nice net code reduction as well as simplified complexity. There is some room for optimization here, for instance with the multiple page mapping, that can be done in one pci_map operation.

[Intel-gfx] [PATCH 34/68] drm/i915: Complete page table structures

Move the remaining members over to the new page table structures. This can be squashed with the previous commit if desire. The reasoning is the same as that patch. I simply felt it is easier to review if split. Signed-off-by: Ben Widawsky Conflicts: drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 38/68] drm/i915: Always dma map page table allocations

There is never a case where we don't want to do it. Since we've broken up the allocations into nice clean helper functions, it's both easy and obvious to do the dma mapping at the same time. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 78

[Intel-gfx] [PATCH 39/68] drm/i915: Consolidate dma mappings

With a little bit of macro magic, and the fact that every page table/dir/etc. we wish to map will have a page, and daddr member, we can greatly simplify and reduce code. The patch introduces an i915_dma_map/unmap which has the same semantics as pci_map_page, but is 1 line, and doesn't require newl

[Intel-gfx] [PATCH 23/68] drm/i915: Rename to GEN8_LEGACY_PDPES

In gen8, 32b PPGTT has always had one "pdp" (it doesn't actually have one, but it resembles having one). The #define was confusing as is, and using "PDPE" is a much better description. sed -i 's/GEN8_LEGACY_PDPS/GEN8_LEGACY_PDPES/' drivers/gpu/drm/i915/*.[ch] Signed-off-by: Ben Widawsky --- dri

[Intel-gfx] [PATCH 26/68] drm/i915: rename map/unmap to dma_map/unmap

Upcoming patches will use the terms map and unmap in references to the page table entries. Having this distinction will really help with code clarity at that point. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions

[Intel-gfx] [PATCH 44/68] drm/i915: Initialize all contexts

The problem is we're going to switch to a new context, which could be the default context. The plan was to use restore inhibit, which would be fine, except if we are using dynamic page tables (which we will). If we use dynamic page tables and we don't load new page tables, the previous page tables

[Intel-gfx] [PATCH 15/68] drm/i915/gen8: Invalidate TLBs before PDP reload

This is a spec requirement for all rings. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_context.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 61b36f9..ef256ae 100644 --- a/drivers/

[Intel-gfx] [PATCH 35/68] drm/i915: Create page table allocators

As we move toward dynamic page table allocation, it becomes much easier to manage our data structures if break do things less coarsely by breaking up all of our actions into individual tasks. This makes the code easier to write, read, and verify. Aside from the dissection of the allocation functi

[Intel-gfx] [PATCH 25/68] drm/i915: s/pd/pdpe, s/pt/pde

The actual correct way to think about this with the new style of page table data structures is as the actual entry that is being indexed into the array. "pd", and "pt" aren't representative of what the operation is doing. The clarity here will improve the readability of future patches. Signed-off

[Intel-gfx] [PATCH 32/68] drm/i915: Page table helpers, and define renames

These page table helpers make the code much cleaner. There is some room to use the arch/x86 header files. The reason I've opted not to is in several cases, the definitions are dictated by the CONFIG_ options which do not always indicate the restrictions in the GPU. While here, clean up the defines

[Intel-gfx] [PATCH 20/68] drm/i915: Make pin global flags explicit

The driver currently lets callers pin global, and then tries to do things correctly inside the function. Doing so has two downsides: 1. It's not possible to exclusively pin to a global, or an aliasing address space. 2. It's difficult to read, and understand. The eventual goal when realized should

[Intel-gfx] [PATCH 17/68] Revert "drm/i915/bdw: Use timeout mode for RC6 on bdw"

This reverts commit 0d68b25e9ceb344fe2f93373b1c0311d33814265. At one time I bisected reset breakage to this patch by using a mesa that is guaranteed to generate a hang when using the fs, and then running the following test case: ./bin/shader_runner tests/shaders/glsl-algebraic-add-zero.shader_te

[Intel-gfx] [PATCH 41/68] drm/i915: Track GEN6 page table usage

Instead of implementing the full tracking + dynamic allocation, this patch does a bit less than half of the work, by tracking and warning on unexpected conditions. The tracking itself follows which PTEs within a page table are currently being used for objects. The next patch will modify this to act

[Intel-gfx] [PATCH 18/68] drm/i915/trace: Fix offsets for 64b

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_trace.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index f5aa006..cbf5521 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/

[Intel-gfx] [PATCH 30/68] drm/i915: Make gen6_write_pdes gen6_map_page_tables

Split out single mappings which will help with upcoming work. Also while here, rename the function because it is a better description - but this function is going away soon. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 39 ++--- 1 file cha

[Intel-gfx] [PATCH 13/68] drm/i915/bdw: Enable full PPGTT

Broadwell is perfectly capable of full PPGTT. I've been using it for some time, and seen no especially ill effects. Signed-off-by: Ben Widawsky Conflicts: drivers/gpu/drm/i915/i915_drv.h --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --gi

[Intel-gfx] [PATCH 45/68] drm/i915: Finish gen6/7 dynamic page table allocation

This patch continues on the idea from the previous patch. From here on, in the steady state, PDEs are all pointing to the scratch page table (as recommended in the spec). When an object is allocated in the VA range, the code will determine if we need to allocate a page for the page table. Similarly

[Intel-gfx] [PATCH 33/68] drm/i915: construct page table abstractions

Thus far we've opted to make complex code requiring difficult review. In the future, the code is only going to become more complex, and as such we'll take the hit now and start to encapsulate things. To help transition the code nicely there is some wasted space in gen6/7. This will be ameliorated

[Intel-gfx] [PATCH 47/68] drm/i915/bdw: pagedirs rework allocation

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++--- 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 65b1c58..5447a99 100644 --- a/drivers/gp

[Intel-gfx] [PATCH 62/68] drm/i915: Plumb sg_iter through va allocation ->maps

As a step towards implementing 4 levels, while not discarding the existing pte map functions, we need to pass the sg_iter through. The current function understands to the page directory granularity. An object's pages may span the page directory, and so using the iter directly as we write the PTEs a

[Intel-gfx] [PATCH 49/68] drm/i915/bdw: Make the pdp switch a bit less hacky

One important part of this patch is we now write a scratch page directory into any unused PDP descriptors. This matters for 2 reasons, first, it's not clear we're allowed to just use 0, or an invalid pointer, and second, we must wipe out any previous contents from the last context. The latter poin

[Intel-gfx] [PATCH 42/68] drm/i915: Extract context switch skip logic

We have some fanciness coming up. This patch just breaks out the logic. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_context.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index

[Intel-gfx] [PATCH 53/68] drm/i915/bdw: begin bitmap tracking

Like with gen6/7, we can enable bitmap tracking with all the preallocations to make sure things actually don't blow up. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 101 +++- drivers/gpu/drm/i915/i915_gem_gtt.h | 12 + 2 files changed

[Intel-gfx] [PATCH 24/68] drm/i915: Split out verbose PPGTT dumping

There often is not enough memory to dump the full contents of the PPGTT. As a temporary bandage, to continue getting valuable basic PPGTT info, wrap the dangerous, memory hungry part inside of a new verbose version of the debugfs file. Also while here we can split out the PPGTT print function so i

[Intel-gfx] [PATCH 51/68] drm/i915: Extract PPGTT param from pagedir alloc

Now that we don't need to trace num_pd_pages, we may as well kill all need for the PPGTT structure in the alloc_pagedirs. This is very useful for when we move to 48b addressing, and the PDP isn't the root of the page table structure. The param is replaced with drm_device, which is an unavoidable w

[Intel-gfx] [PATCH 31/68] drm/i915: Range clearing is PPGTT agnostic

Therefore we can do it from our general init function. Eventually, I hope to have a lot more commonality like this. It won't arrive yet, but this was a nice easy one. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) di

[Intel-gfx] [PATCH 48/68] drm/i915/bdw: pagetable allocation rework

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 - drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++ 2 files changed, 39 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_g

[Intel-gfx] [PATCH 16/68] drm/i915: Remove false assertion in ppgtt_release

Originally the thought for the assertion was that if there are no real VMAs (died during execbuf), or there is only 1 VMA, but the VMA is on the active list, it's a bug. The former case is pretty obvious. The later case simply meant to assert the context unref/object retire interactions were workin

[Intel-gfx] [PATCH 43/68] drm/i915: Track page table reload need

This patch was formerly known as, "Force pd restore when PDEs change, gen6-7." I had to change the name because it is needed for GEN8 too. The real issue this is trying to solve is when a new object is mapped into the current address space. The GPU does not snoop the new mapping so we must do the

[Intel-gfx] [PATCH 21/68] drm/i915: Split out aliasing binds

This patch finishes off actually separating the aliasing and global finds. Prior to this, all global binds would be aliased. Now if aliasing binds are required, they must be explicitly asked for. So far, we have no users of this outside of execbuf - but Mika has already submitted a patch requiring

[Intel-gfx] [PATCH 54/68] drm/i915/bdw: Dynamic page table allocations

This finishes off the dynamic page tables allocations, in the legacy 3 level style that already exists. Most everything has already been setup to this point, the patch finishes off the enabling by setting the appropriate function pointers. Zombie tracking: This could be a separate patch, but I fou

[Intel-gfx] [PATCH 58/68] drm/i915/bdw: Add ppgtt info for dynamic pages

Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_debugfs.c | 52 - drivers/gpu/drm/i915/i915_gem_gtt.c | 33 +++ drivers/gpu/drm/i915/i915_gem_gtt.h | 9 +++ 3 files changed, 82 insertions(+), 12 deletions(-) diff --git a/driv

[Intel-gfx] [PATCH 40/68] drm/i915: Always dma map page directory allocations

Similar to the patch a few back in the series, we can always map and unmap page directories when we do their allocation and teardown. Page directory pages only exist on gen8+, so this should only effect behavior on those platforms. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gt

[Intel-gfx] [PATCH 22/68] drm/i915: fix gtt_total_entries()

It's useful to have it not as a macro for some upcoming work. Generally since we try to avoid macros anyway, I think it doesn't hurt to put this as its own patch. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c| 4 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h| 7 +--

[Intel-gfx] [PATCH 56/68] drm/i915/bdw: Abstract PDP usage

Up until now, ppgtt->pdp has always been the root of our page tables. Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs. In preparation for 4 level page tables, we need to stop use ppgtt->pdp directly unless we know it's what we want. The future structure will use ppgtt->pml4 for the top l

  1   2   >