[Intel-gfx] [PATCH 1/3] drm/i915: Add PTE encoding function to the gtt/ppgtt vtables.

Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly different page table entry formats. Rather than polluting one function with generation checks, simply use a function pointer and set up the correct PTE encoding function at startup. v2: Move the gen6_gtt_pte_t typedef to i915_drv.h s

[Intel-gfx] [PATCH 2/3] drm/i915: Fix page table entries for Bay Trail.

On Bay Trail, bit 1 means "writeable by the GPU." Failing to set that means basically anything using the GPU will cause hangs. v2: Drop accidental inline keyword on byt_pte_encode. Signed-off-by: Kenneth Graunke Reviewed-by: Jani Nikula [v1] Tested-by: Daniel Leung [v1] --- drivers/gpu/drm/i

[Intel-gfx] [PATCH 3/3] drm/i915: Split out Haswell code from gen6_pte_encode.

Now that we have function pointers, it's cleaner to just create a new per-platform PTE encoding function. This should be identical in behavior to the previous code. v2: Drop accidental inline keyword on hsw_pte_encode. Signed-off-by: Kenneth Graunke Reviewed-by: Jani Nikula [v1] Tested-by: Dan

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add PTE encoding function to the gtt/ppgtt vtables.

On the series, Reviewed-by: Jani Nikula On Mon, 22 Apr 2013, Kenneth Graunke wrote: > Sandybridge/Ivybridge, Bay Trail, and Haswell all have slightly > different page table entry formats. Rather than polluting one function > with generation checks, simply use a function pointer and set up th

Re: [Intel-gfx] [PATCH] drm/i915: remove redundant (and incorrect!) dither enable for VLV

On Fri, 19 Apr 2013, Jesse Barnes wrote: > We already enable dithering above if needed, and we definitely shouldn't > be enabling the pipe at this point, so just drop this whole block. This gets rid of the pipe enabled when expected off backtrace I kept having. Tested-by: Jani Nikula > > Signe

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add PTE encoding function to the gtt/ppgtt vtables.

On Mon, Apr 22, 2013 at 11:13:18AM +0300, Jani Nikula wrote: > > On the series, > > Reviewed-by: Jani Nikula All merged, thanks for the patches&review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [Intel-gfx] [PATCH 13/15] drm/i915: move fdi lane configuration checks ahead

On Fri, Apr 19, 2013 at 11:24:45AM +0200, Daniel Vetter wrote: > This nicely allows us to drop some hacks which have only been used > to work around modeset failures due to lack of fdi lanes. > > v2: Implement proper checking for Haswell platforms - the fdi link to > the LPT PCH has only 2 lanes.

Re: [Intel-gfx] [PATCH] drm/i915: shovel compute clock into crtc->config.dpll on ilk

On Sat, Apr 20, 2013 at 05:19:46PM +0200, Daniel Vetter wrote: > This was somehow lost in the pipe_config->dpll introduction in > > commit f47709a9502f3715cc488b788ca91cf0c142b1b1 > Author: Daniel Vetter > Date: Thu Mar 28 10:42:02 2013 +0100 > > drm/i915: create pipe_config->dpll for cloc

Re: [Intel-gfx] [PATCH] drm/i915: avoid full modeset when changing the color range properties

On Fri, Apr 19, 2013 at 05:26:27PM +0200, Daniel Vetter wrote: > Automatic color range selection was added in > > commit 55bc60db5988c8366751d3d04dd690698a53412c > Author: Ville Syrjälä > Date: Thu Jan 17 16:31:29 2013 +0200 > > drm/i915: Add "Automatic" mode for the "Broadcast RGB" proper

Re: [Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum after entering RC6

On Fri, Apr 19, 2013 at 10:22:45AM -0700, Jesse Barnes wrote: > On VLV, the Punit doesn't automatically drop the GPU to it's minimum > voltage level when entering RC6, so we arm a timer to do it for us from > the RPS interrupt handler. It'll generally only fire when we go idle > (or if for some re

Re: [Intel-gfx] [PATCH] drm/i915: Decode RING_BUFFER_HEAD in error state

On Sun, Apr 21, 2013 at 04:01:19PM -0700, Ben Widawsky wrote: > I consistently forget how to decode the HEAD pointer. If we put it in > the error state, one doesn't need to look in docs to find the relevant > info. > > Signed-off-by: Ben Widawsky Turn the offset into an address and that would be

Re: [Intel-gfx] [PATCH v3 05/16] drm/i915: track ring progression using seqnos

Ben Widawsky writes: > On Sat, Apr 20, 2013 at 11:43:51AM -0700, Ben Widawsky wrote: >> On Thu, Apr 04, 2013 at 06:32:37PM +0300, Mika Kuoppala wrote: >> > Instead of relying in acthd, track ring seqno progression >> > to detect if ring has hung. >> > >> > v2: put hangcheck stuff inside struct (

[Intel-gfx] [PATCH] drm/i915: Remove unused power well register definitions

Those registers are not used, let's not keep them around for no reason. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 60e0e19..a766d86 100644 --- a/

[Intel-gfx] Power well issue could not be reproduced with drm-intel-next branch

Hi Daniel/Paulo, In order to verify an RFC patch to fix the power well issue, I'm trying to reproduce it on my Haswell ULT C stepping board, with " drm-intel-next" branch, the last commit is: commit 80ad9206c0d863832bc5f6008c4d1868d1df8e70 Author: Ville Syrjälä Date: Fri Apr 19 14:36:51 2013

[Intel-gfx] [RFC][PATCH] drm/i915: Make data/link N value power of two

From: Ville Syrjälä The BIOS uses power of two values for the data/link N value. Follow suit to make the Zotac DP to dual-HDMI dongle work. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402 Signed-off-by: Ville Syrjälä --- Warning: I've only tested this with the Zotac dongle hooked

Re: [Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum after entering RC6

On Mon, 22 Apr 2013 14:39:17 +0300 Ville Syrjälä wrote: > On Fri, Apr 19, 2013 at 10:22:45AM -0700, Jesse Barnes wrote: > > On VLV, the Punit doesn't automatically drop the GPU to it's minimum > > voltage level when entering RC6, so we arm a timer to do it for us from > > the RPS interrupt handle

[Intel-gfx] [PATCH] drm/i915: avoid full modeset when changing the color range properties

Automatic color range selection was added in commit 55bc60db5988c8366751d3d04dd690698a53412c Author: Ville Syrjälä Date: Thu Jan 17 16:31:29 2013 +0200 drm/i915: Add "Automatic" mode for the "Broadcast RGB" property but that removed the check to avoid a full modeset if the value is unchan

[Intel-gfx] [PATCH] drm/i915: avoid full modeset when changing the color range properties

Automatic color range selection was added in commit 55bc60db5988c8366751d3d04dd690698a53412c Author: Ville Syrjälä Date: Thu Jan 17 16:31:29 2013 +0200 drm/i915: Add "Automatic" mode for the "Broadcast RGB" property but that removed the check to avoid a full modeset if the value is unchan

Re: [Intel-gfx] [PATCH] drm/i915: shovel compute clock into crtc->config.dpll on ilk

On Mon, Apr 22, 2013 at 02:13:44PM +0300, Ville Syrjälä wrote: > On Sat, Apr 20, 2013 at 05:19:46PM +0200, Daniel Vetter wrote: > > This was somehow lost in the pipe_config->dpll introduction in > > > > commit f47709a9502f3715cc488b788ca91cf0c142b1b1 > > Author: Daniel Vetter > > Date: Thu Mar

[Intel-gfx] [PATCH] drm/i915: move fdi lane configuration checks ahead

This nicely allows us to drop some hacks which have only been used to work around modeset failures due to lack of fdi lanes. v2: Implement proper checking for Haswell platforms - the fdi link to the LPT PCH has only 2 lanes. Note that we already filter out impossible modes in intel_crt_mode_valid.

Re: [Intel-gfx] [PATCH] drm/i915: Decode RING_BUFFER_HEAD in error state

On Mon, Apr 22, 2013 at 02:16:34PM +0100, Chris Wilson wrote: > On Sun, Apr 21, 2013 at 04:01:19PM -0700, Ben Widawsky wrote: > > I consistently forget how to decode the HEAD pointer. If we put it in > > the error state, one doesn't need to look in docs to find the relevant > > info. > > > > Signe

Re: [Intel-gfx] [RFC][PATCH] drm/i915: Make data/link N value power of two

On Mon, Apr 22, 2013 at 05:23:50PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The BIOS uses power of two values for the data/link N value. > > Follow suit to make the Zotac DP to dual-HDMI dongle work. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402 >

Re: [Intel-gfx] [RFC][PATCH] drm/i915: Make data/link N value power of two

On Mon, Apr 22, 2013 at 05:23:50PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The BIOS uses power of two values for the data/link N value. > > Follow suit to make the Zotac DP to dual-HDMI dongle work. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402 >

Re: [Intel-gfx] [PATCH] drm/i915: Decode RING_BUFFER_HEAD in error state

On Mon, Apr 22, 2013 at 05:17:41PM +0200, Daniel Vetter wrote: > On Mon, Apr 22, 2013 at 02:16:34PM +0100, Chris Wilson wrote: > > On Sun, Apr 21, 2013 at 04:01:19PM -0700, Ben Widawsky wrote: > > > I consistently forget how to decode the HEAD pointer. If we put it in > > > the error state, one doe

Re: [Intel-gfx] [RFC][PATCH] drm/i915: Make data/link N value power of two

On Mon, Apr 22, 2013 at 05:23:50PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > The BIOS uses power of two values for the data/link N value. > > Follow suit to make the Zotac DP to dual-HDMI dongle work. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49402 >

[Intel-gfx] Try to make the device info flags a bit more maintainable

Hi, We had a few places (3) to update every time we wanted to add a device info flag, somewhat error prone. With this series we just need to touch DEV_INFO_FOR_EACH_FLAG() to add a flag (patches 1-3). On top of that, I add two more flags, has_ddi (patch 4) and has_fpga_dbg (patches 5/6), flags th

[Intel-gfx] [PATCH 1/6] drm/i915: Turn DEV_INFO_FLAGS into for foreach style macro

DEV_INFO_FOR_FLAG() now takes 2 parameters: • A function to apply to the flag • A separator This will allow us to use the macro twice in the DRM_DEBUG_DRIVER() call of i915_dump_device_info(). Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_debugfs.c | 8 +++--- drivers/gpu/drm

[Intel-gfx] [PATCH 2/6] drm/i915: Replace the line of %s by a DEV_INFO_FOR_EACH_FLAG() invocation

This way, when adding a device flag we don't have to manually maintain that list. Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_dma.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 8ac8d

[Intel-gfx] [PATCH 3/6] drm/i915: Use DEV_INFO_FOR_EACH_FLAG() to declare flags as well

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_drv.h | 31 +++ 1 file changed, 7 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 725d53d..4239263 100644 --- a/drivers/gpu/drm/i915/i915_dr

[Intel-gfx] [PATCH 4/6] drm/i915: Turn HAS_DDI() into a device_info flag

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9ebe895..564d4c6 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 5/6] drm/i915: Introduce HAS_FPGA_DBG_UNCLAIMED()

Let's introduce one more of those orthogonal feature macros. This should hopefully make the code more readable and make things easier for new platform enabling. This time, HAS_FPGA_DBG_UNCLAIMED() is true for platforms that have bit 31 of FPGA_DBG able to signal unclaimed writes. Signed-off-by: D

[Intel-gfx] [PATCH 6/6] drm/i915: Turn HAS_FPGA_DBG_UNCLAIMED into a device_info flag

Signed-off-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_drv.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 896b904..624cdfc 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum after entering RC6 v2

On VLV, the Punit doesn't automatically drop the GPU to it's minimum voltage level when entering RC6, so we arm a timer to do it for us from the RPS interrupt handler. It'll generally only fire when we go idle (or if for some reason there's a long delay between RPS interrupts), but won't be re-arm

Re: [Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum after entering RC6 v2

On Mon, Apr 22, 2013 at 7:54 PM, Jesse Barnes wrote: > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2557926..4669d8c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2545,6 +2545,9 @@ static void gen6_disable_rps

[Intel-gfx] [PATCH 4/4] intel_error_decode: Future proof ring count

Signed-off-by: Ben Widawsky --- tools/intel_error_decode.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c index 96aaf72..d2e91e7 100644 --- a/tools/intel_error_decode.c +++ b/tools/intel_error_decode.c @@ -283,6 +283,

[Intel-gfx] [PATCH 2/4] intel_error_decode: HEAD stuff

Show the decoded HEAD value, as well as print the calculated head offset per ringbuffer. This will be superceded in the next commit, but I think more info is better. Signed-off-by: Ben Widawsky --- tools/intel_error_decode.c | 22 -- 1 file changed, 20 insertions(+), 2 delet

[Intel-gfx] [PATCH 1/4] intel_error_decode: Whitespacing fix

The rest of igt has moved to kernel coding style. People had already been not conforming with the existing formatting in error decode, so we may as well fix it. This addresses two primary issues, tabbing (remove spaces), and space after function in function call. I may have missed some of the latt

[Intel-gfx] [PATCH 3/4] intel_error_decode: Fix ACTHD/HEAD mess with libdrm

Easy to do with the stuff in place before this. Signed-off-by: Ben Widawsky --- tools/intel_error_decode.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c index e29ee1e..96aaf72 100644 --- a/tools/int

Re: [Intel-gfx] [PATCH 4/4] intel_error_decode: Future proof ring count

On Mon, Apr 22, 2013 at 12:00:57PM -0700, Ben Widawsky wrote: > Signed-off-by: Ben Widawsky Fold this into the earlier patch. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http:/

Re: [Intel-gfx] [PATCH 2/4] intel_error_decode: HEAD stuff

On Mon, Apr 22, 2013 at 12:00:55PM -0700, Ben Widawsky wrote: > Show the decoded HEAD value, as well as print the calculated head offset > per ringbuffer. Give us an example! -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mai

Re: [Intel-gfx] [PATCH 3/4] intel_error_decode: Fix ACTHD/HEAD mess with libdrm

On Mon, Apr 22, 2013 at 12:00:56PM -0700, Ben Widawsky wrote: > Easy to do with the stuff in place before this. This looks like it will make me happier, thanks. With just a couple of minor changes, Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___

Re: [Intel-gfx] [PATCH 3/4] intel_error_decode: Fix ACTHD/HEAD mess with libdrm

On Mon, Apr 22, 2013 at 12:00:56PM -0700, Ben Widawsky wrote: > Easy to do with the stuff in place before this. > > Signed-off-by: Ben Widawsky My assumptions on ordering of the error dump were incorrect. Ie. this patch is no good. Working on a fix when I have some time. [snip] -- Ben Widawsk

Re: [Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum after entering RC6 v2

Ouch good catch. I'll put the cancelation outside the scope of the lock.  -- Jesse Barnes, Intel Open Source Technology Center Original message From: Daniel Vetter Date: 04/22/2013 11:52 AM (GMT-08:00) To: Jesse Barnes Cc: intel-gfx Subject: Re: [Intel-gfx] [PATCH] dr

[Intel-gfx] [PATCH] drm/i915: fix locking around punit access in cur_delayinfo for VLV

We need to hold the rps lock around punit access. Reported-by: Kenneth Graunke Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_debugfs.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 367b534..d

[Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum after entering RC6 v3

On VLV, the Punit doesn't automatically drop the GPU to it's minimum voltage level when entering RC6, so we arm a timer to do it for us from the RPS interrupt handler. It'll generally only fire when we go idle (or if for some reason there's a long delay between RPS interrupts), but won't be re-arm

[Intel-gfx] [PATCH 2/3] [v2] intel_error_decode: HEAD stuff

Show the decoded HEAD value, as well as print the calculated head offset per ringbuffer. This will be superceded in the next commit, but that patch is way more complicated than this one (read: error prone), so I want this here. Example: ringbuffer (blitter ring) at 0x00044000; HEAD points to: 0x0

[Intel-gfx] [PATCH 3/3] [v3] intel_error_decode: Fix ACTHD/HEAD mess with libdrm

This patch is an enormous mess, and I'd be fine if people didn't want it. However I have made the code do what we want at least on the two error dumps I've tried. The way that it works is it attempts to identify which ACTHD belongs to the ring, or batch, and add the appropriate offset as necessary

[Intel-gfx] [PATCH 1/3] [REPOST] intel_error_decode: Whitespacing fix

The rest of igt has moved to kernel coding style. People had already been not conforming with the existing formatting in error decode, so we may as well fix it. This addresses two primary issues, tabbing (remove spaces), and space after function in function call. I may have missed some of the latt