On Wed, 26 Sep 2012, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index a8a81d1..aee6151 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/d
On Wed, 26 Sep 2012, Chris Wilson wrote:
> The intention was to allow the caller to avoid a failure to queue a
> request having already written commands to the ring. However, this is a
> moot point as the i915_add_request() can fail for other reasons than a
> mere allocation failure and those fail
As SandyBridge returns garbage when decoding certain addresses through
the GTT (all memory below 1MiB and a very small number of individual
pages) we need to prevent the GPU from utilizing those pages. The
ultimate goal would be to prevent our allocator from handing us those
pages, but that is a lo
This is great news. I will watch for the udpate.
Charlie
-Original Message-
From: Xiang, Haihao [mailto:haihao.xi...@intel.com]
Sent: Wednesday, September 26, 2012 9:17 PM
To: Charlie Good
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] Question regarding libva encoding
Th
FWIW, I am able to get graphics on the screen now - Apparently only the
hdmi port works on HSW right now - which I was unaware of.
This stack was a red-herring to that problem.
Thanks for the response.
Ben
On Thu, Sep 27, 2012 at 2:34 AM, Daniel Vetter wrote:
> On Thu, Sep 27, 2012 at 06:32:06
On Thu, Sep 27, 2012 at 10:39:53AM +0300, Jani Nikula wrote:
> On Wed, 26 Sep 2012, Chris Wilson wrote:
> > The intention was to allow the caller to avoid a failure to queue a
> > request having already written commands to the ring. However, this is a
> > moot point as the i915_add_request() can f
On Wed, Sep 26, 2012 at 11:40:26AM -0700, Ben Widawsky wrote:
> On Wed, 26 Sep 2012 13:51:01 +0200
> Daniel Vetter wrote:
>
> > On Sat, Sep 22, 2012 at 01:58:37PM -0700, Ben Widawsky wrote:
> > > On 2012-09-22 11:05, Daniel Vetter wrote:
> > > >And a quick comment on your approach here: I'm not t
On Thu, Sep 27, 2012 at 09:27:57AM +0100, Chris Wilson wrote:
> As SandyBridge returns garbage when decoding certain addresses through
> the GTT (all memory below 1MiB and a very small number of individual
> pages) we need to prevent the GPU from utilizing those pages. The
> ultimate goal would be
On Thu, Sep 27, 2012 at 02:14:22PM +0200, Daniel Vetter wrote:
> On Thu, Sep 27, 2012 at 09:27:57AM +0100, Chris Wilson wrote:
> > As SandyBridge returns garbage when decoding certain addresses through
> > the GTT (all memory below 1MiB and a very small number of individual
> > pages) we need to pr
On Thu, 27 Sep 2012 14:16:11 +0200, Daniel Vetter wrote:
> On Thu, Sep 27, 2012 at 02:14:22PM +0200, Daniel Vetter wrote:
> > On Thu, Sep 27, 2012 at 09:27:57AM +0100, Chris Wilson wrote:
> > > As SandyBridge returns garbage when decoding certain addresses through
> > > the GTT (all memory below 1
On Thu, Sep 20, 2012 at 11:17:51AM +0200, Daniel Vetter wrote:
> On Thu, Sep 20, 2012 at 10:56 AM, Chris Wilson
> wrote:
> > We need to wait for pending operations on the CRTC to retire before we
> > can modify the CRTC. For example, if userspace has queued a batch that
> > uses a WAIT_FOR_EVENT
On 9/26/2012 7:54 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:34PM +0530, Vijay Purushothaman wrote:
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Also use
i9xx_update_pll to program the correct DPLL seque
On 9/26/2012 8:08 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:37PM +0530, Vijay Purushothaman wrote:
Fixed min, max vco limits for VLV HDMI. Also fixed correct register
offset for VLV_VIDEO_DIP_CTL_A
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben
On 9/26/2012 8:10 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
From: "Bhat, Gajanan"
Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
programming to vlv_update_pll function. With all the changes multi
display (clone, exte
On 9/26/2012 8:19 PM, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_se
On 9/27/2012 12:48 PM, Jani Nikula wrote:
On Wed, 26 Sep 2012, Daniel Vetter wrote:
On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a8a81d1..aee6151 100644
--- a/drivers/gpu/drm
This patch set enables all supported display interfaces like HDMI, DisplayPort
and eDP for Valleyview. This also enables support for multi-display
configurations.
v2: Addressed review comments from Daniel and Jani Nikula.
Gajanan Bhat (1):
drm/i915: Add eDP support for Valleyview
Vijay Purush
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_dp.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
Fixed SDVOB and SDVOC bit definitions for Valleyview.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_irq.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c |6 +++---
drivers/gpu/drm/i915/intel_dp.c |5 +
2 files changed, 8 insertions(+), 3 deleti
Added DPIO data lane register definitions for Valleyview
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a828
In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.
Cleaned up DPLL calculations for Valleyview to support multi display
configurations.
v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as
separate
patc
Temporary work around to avoid spurious crt hotplug interrupts.
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
---
drivers/gpu/drm/i915/intel_crt.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
i
From: Gajanan Bhat
Eventhough Valleyview display block is derived from Cantiga, VLV
supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
v2: use different DPIO_DIVISOR values for VGA, DP and eDP
v3: fix DPIO value calculation to use same values for all display
interfaces
v4: removed un
Fixed correct min, max vco limits and dip ctl reg
Signed-off-by: Vijay Purushothaman
Signed-off-by: Gajanan Bhat
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
drivers/gpu/drm/i915/intel_display.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
dif
PPS register offsets have changed in Valleyview.
Signed-off-by: Gajanan Bhat
Signed-off-by: Vijay Purushothaman
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gpu/drm/i915/intel_dp.c | 122 +++
2 files changed, 93 insert
On Thu, Sep 27, 2012 at 07:08:41PM +0530, Vijay Purushothaman wrote:
> On 9/26/2012 8:19 PM, Daniel Vetter wrote:
> >On Wed, Sep 26, 2012 at 04:31:46PM +0200, Daniel Vetter wrote:
> >>On Wed, Sep 26, 2012 at 07:07:35PM +0530, Vijay Purushothaman wrote:
> >>>Eventhough Valleyview display block is de
On Thu, 27 Sep 2012 19:13:01 +0530
Vijay Purushothaman wrote:
> Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
> This enables the aux transactions in Valleyview.
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/intel_dp
On Thu, 27 Sep 2012 19:13:02 +0530
Vijay Purushothaman wrote:
> Fixed SDVOB and SDVOC bit definitions for Valleyview.
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_irq.c |6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
On Thu, 27 Sep 2012 19:13:03 +0530
Vijay Purushothaman wrote:
> Added DPIO data lane register definitions for Valleyview
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_reg.h |8
> 1 file changed, 8 insertions(+)
>
> diff --
On Thu, 27 Sep 2012 19:13:04 +0530
Vijay Purushothaman wrote:
> m n tu register offset has changed in Valleyview. Also fixed DP limit
> frequencies.
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/intel_display.c |6 +++---
> drivers/gpu/d
On Thu, 27 Sep 2012 19:13:05 +0530
Vijay Purushothaman wrote:
> Temporary work around to avoid spurious crt hotplug interrupts.
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Gajanan Bhat
> ---
> drivers/gpu/drm/i915/intel_crt.c |7 +++
> 1 file changed, 7 insertions(+)
>
>
On Thu, 27 Sep 2012 19:13:06 +0530
Vijay Purushothaman wrote:
> In valleyview voltageswing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric.
>
> Cleaned up DPLL calculations for Valleyview to support multi display
> configurations.
>
> v2: Based
On Thu, 27 Sep 2012 19:13:07 +0530
Vijay Purushothaman wrote:
> From: Gajanan Bhat
>
> Eventhough Valleyview display block is derived from Cantiga, VLV
> supports eDP. So, added eDP checks in i9xx_crtc_mode_set path.
>
> v2: use different DPIO_DIVISOR values for VGA, DP and eDP
> v3: fix DPIO
On Thu, 27 Sep 2012 19:13:09 +0530
Vijay Purushothaman wrote:
> Fixed correct min, max vco limits and dip ctl reg
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Gajanan Bhat
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_reg.h |2 +-
> drivers/gpu/drm/i915/
On Thu, 27 Sep 2012 19:13:08 +0530
Vijay Purushothaman wrote:
> PPS register offsets have changed in Valleyview.
>
> Signed-off-by: Gajanan Bhat
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_reg.h |9 +++
> drivers/gpu/drm/i915/intel
On Thu, 27 Sep 2012 19:13:05 +0530
Vijay Purushothaman wrote:
> Temporary work around to avoid spurious crt hotplug interrupts.
>
> Signed-off-by: Vijay Purushothaman
> Signed-off-by: Gajanan Bhat
> ---
> drivers/gpu/drm/i915/intel_crt.c |7 +++
> 1 file changed, 7 insertions(+)
>
>
On Wed, 26 Sep 2012 14:06:36 +0200
Daniel Vetter wrote:
> On Mon, Sep 17, 2012 at 05:10:15PM -0700, Ben Widawsky wrote:
> > I do not currently have a VLV to test this on, but hopefully it only
> > removes information from debugfs, sysfs, and prevents enabling an
> > unsupported mode.
> >
> > CC:
On Thu, Sep 27, 2012 at 5:34 PM, Ben Widawsky wrote:
> On Wed, 26 Sep 2012 14:06:36 +0200
> Daniel Vetter wrote:
>
>> On Mon, Sep 17, 2012 at 05:10:15PM -0700, Ben Widawsky wrote:
>> > I do not currently have a VLV to test this on, but hopefully it only
>> > removes information from debugfs, sysf
On Thu, Sep 27, 2012 at 08:26:15AM -0700, Jesse Barnes wrote:
> On Thu, 27 Sep 2012 19:13:08 +0530
> Vijay Purushothaman wrote:
>
> > PPS register offsets have changed in Valleyview.
> >
> > Signed-off-by: Gajanan Bhat
> > Signed-off-by: Vijay Purushothaman
> > Signed-off-by: Ben Widawsky
> >
On Wed, 26 Sep 2012 10:34:00 -0700
Ben Widawsky wrote:
> There is a special mechanism for communicating with the PCU already
> being used for the ring frequency stuff. As we'll be needing this for
> other commands, extract it now to make future code less error prone and
> the current code more re
On Wed, 26 Sep 2012 10:34:01 -0700
Ben Widawsky wrote:
> BIOS should be setting the minimum voltage for rc6 to be 450mV. Old or
> buggy BIOSen may not be doing this, so we correct it for them. Ideally
> customers should update the BIOS as only it would know the optimal
> values for the platform,
On Wed, 26 Sep 2012 10:34:02 -0700
Ben Widawsky wrote:
> CC: Jesse Barnes
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i9
This series is the second revison of:
http://lists.freedesktop.org/archives/intel-gfx/2012-September/020457.html
It changes the way 3d modes are exposed to user-space:
- An "expose 3D modes" property can be installed on connectors that support
stereo 3D
- User space can indicate through that
From: Damien Lespiau
The "expose 3D modes" property can be attached to connectors to allow
user space to indicate it can deal with 3D modes and that the drm driver
should expose those 3D modes.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/drm_crtc.c | 35 ++
From: Damien Lespiau
When scanning out a 3D framebuffer, send the corresponding infoframe to
the HDMI sink.
See http://www.hdmi.org/manufacturer/specification.aspx for details.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_drv.h | 14 +++
drivers/gpu/drm/i915/intel_hd
From: Damien Lespiau
For now, let's just look at the 3D_present flag of the CEA HDMI vendor
block to detect if the sink supports a small list of then mandatory 3D
formats.
See the HDMI 1.4a 3D extraction for detail:
http://www.hdmi.org/manufacturer/specification.aspx
Signed-off-by: Damien Les
From: Damien Lespiau
When dumping the details of a mode, let's add the 3D formats the mode
supports.
Signed-off-by: Damien Lespiau
---
lib/drmtest.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 8df9797..4d5a67c 100644
--
From: Damien Lespiau
Now that modes have flags to describe which 3d formats the sink
supports, it's time to test them.
The new test cycles through the supported 3D formats and paint 3D
stereoscopic images taken from publicly available samples:
http://www.quantumdata.com/apps/3D/sample_BMP.asp
This was meant to be the purpose of the
intel_crtc_wait_for_pending_flips() function which is called whilst
preparing the CRTC for a modeset or before disabling. However, as Ville
Syrjala pointed out, we set the pending flip notification on the old
framebuffer that is no longer attached to the CRTC
On Fri, Sep 28, 2012 at 4:05 AM, Jesse Barnes wrote:
> On Wed, 26 Sep 2012 10:34:01 -0700
> Ben Widawsky wrote:
>
>> BIOS should be setting the minimum voltage for rc6 to be 450mV. Old or
>> buggy BIOSen may not be doing this, so we correct it for them. Ideally
>> customers should update the BIOS
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