On Mon, Oct 31, 2011 at 23:42, James R. Leu wrote:
> I do not use hibernate, I have my lid close set to suspend.
> Up until I upgraded to 3.2.0 kernel (rawhide) my suspend/wakup cycles
> had been stable.
>
>From what version have you upgraded?
Could you try to bisect it, to find the commit whic
I went form 3.1.0 to 3.2.0 (fedora rawhid RPMs).
I will pull the source RPMs and figure out what git commit they
are are based off of and then try a bisect.
On Tue, Nov 01, 2011 at 08:37:42AM -0200, Eugeni Dodonov wrote:
> On Mon, Oct 31, 2011 at 23:42, James R. Leu wrote:
> I do not use hi
Hi Christopher,
Sorry I'm just back from traveling..
On Fri, Oct 28, 2011 at 03:54:23AM +0800, Christopher White wrote:
> There appears to be some issues with the patch? I'm on SandyBridge and
> using the HD3000's HDMI.
>
> I've now tried manually merging the ELD patch (both files Wu Fengguang
Hi Jesse,
I hope the function of snb_update_plane can handle crtx_x<0 or crtc_y<0 just
like my patch.
What do you think about it?
Thanks and best regards.
Hai Lan
>From 160c899739e7d07f273de889cc889316837d0790 Mon Sep 17 00:00:00 2001
From: Hai Lan
Date: Tue, 1 Nov 2011 21:30:08 -0400
Subject
On Sun, Oct 30, 2011 at 17:12, Daniel Vetter wrote:
> ... and add a helpr function for the places where we want a flag.
>
> This way we can use ring->id to index into arrays.
>
> v2: Resurrect the missing beautification-space Chris Wilson noted.
> I'm moving this space around because I'll reuse r
On Sun, Oct 30, 2011 at 17:12, Daniel Vetter wrote:
> In the pre-gem days with non-existing hangcheck and gpu reset code,
> this timeout of 3 seconds was pretty important to avoid stuck
> processes.
>
> But now we have the hangcheck code in gem that goes to great length
> to ensure that the gpu i
On Fri, Oct 28, 2011 at 6:56 PM, Keith Packard wrote:
> Kernels with no iommu support cannot ever need the Ironlake
> work-around, so never enable it in that case.
>
> Might be better to completely remove the work-around from the kernel
> in this case?
>
While I'm not offended by this patch, I am
On 11/1/11 12:36 PM, Wu Fengguang wrote:
Hi Christopher,
Sorry I'm just back from traveling..
No worries, I am not in any hurry, and I hope you had a great holiday! :-)
On Fri, Oct 28, 2011 at 03:54:23AM +0800, Christopher White wrote:
There appears to be some issues with the patch? I'm on S
Cleanups recommended by Dave Airlie.
Cc: Keith Packard
Signed-off-by: Ben Widawsky
---
drivers/char/agp/intel-agp.h |6 ++
drivers/char/agp/intel-gtt.c |7 ---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-a
On Tue, 1 Nov 2011 11:29:49 -0700
Ben Widawsky wrote:
> Cleanups recommended by Dave Airlie.
>
> Cc: Keith Packard
> Signed-off-by: Ben Widawsky
> ---
> drivers/char/agp/intel-agp.h |6 ++
> drivers/char/agp/intel-gtt.c |7 ---
> 2 files changed, 10 insertions(+), 3 deletions
Hi Christopher,
> The log does confirm that the drm_edid_to_eld function is running, and
> that we're not far from a solution:
> [ 21.061417] [drm:drm_edid_to_eld], ELD monitor TX-SR607
> [ 21.061421] [drm:drm_edid_to_eld], ELD size 13, SAD count 8
It looks all sane to this point.
> As for
Use 0x1000 as the default backlight PWM max value and period. This is
passed in as a module parameter to i915_drv and is used to program the
PWM registers. It can be set to other values based on the needs of each
system.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_reg.h|1 +
Sorry, this is the wrong patch, please disregard.
On Tue, Nov 1, 2011 at 6:58 PM, Simon Que wrote:
> Use 0x1000 as the default backlight PWM max value and period. This is
> passed in as a module parameter to i915_drv and is used to program the
> PWM registers. It can be set to other values bas
Hi, Jesse.
Jesse Barnes virtuousgeek.org> writes:
>
> On Mon, 31 Oct 2011 11:40:57 + (UTC)
> Inki Dae gmail.com> wrote:
> > below is my simple idea.
> > 1. user requests buffer allocation with pixel format and resolution
through
> > gem framework.
> > 2. gem framework checks pixel format
Use 0x1000 as the default backlight PWM max value and period. This is
passed in as a module parameter to i915_drv and is used to program the
PWM registers. It can be set to other values based on the needs of each
system.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_drv.c|3 ++
Again, adding arbitrary constants without any explanation for why you're
making this the default really isn't acceptable. We have no way to
determine whether fixing one machine is worth making things worse for
another.
--
Matthew Garrett | mj...@srcf.ucam.org
__
Hi,
I am trying to run multiple mpg files simultaneously from the command line
using "mplayer" and "libva".
The videos run fine for a few seconds or so but then the display
flickers and
becomes black and ultimately the system hangs.
This is the log given by mplayer on commad line:
"Too many v
Hi, Jesse.
drm_plane structure has format_types and format_conunt that they was set at
booting time. but they aren't used anywhere. at intel_update_plane(), I guess
they could be used to check if the format type(fb->pixel_format) from setplane
() is supported or not, comparing to plane->format_t
On Tue, Nov 1, 2011 at 8:45 PM, Wu Fengguang wrote:
> Hi Christopher,
>
>> The log does confirm that the drm_edid_to_eld function is running, and
>> that we're not far from a solution:
>> [ 21.061417] [drm:drm_edid_to_eld], ELD monitor TX-SR607
>> [ 21.061421] [drm:drm_edid_to_eld], ELD size 1
Here's a patch sequence which makes my PCH-connected eDP panel
work. The main bug was a pile of places where the driver was
incorrectly treating a PCH connected eDP panel like a CPU connected
eDP panel, setting incorrect bits in the DP_CTL register and failing
to configure the TRANS_DP_CTL register
Every usage of PCH_PP_CONTROL sets the PANEL_UNLOCK_REGS value to
ensure that writes will be respected, move this to a common function
to make the driver cleaner.
No functional changes.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_dp.c | 37 +++--
Make sure the sequence of operations in all three functions makes
sense:
1) The backlight must be off unless the screen is running
2) The link must be running to turn the eDP panel on/off
3) The CPU eDP PLL must be running until everything is off
Signed-off-by: Keith Packard
---
drivers/gpu/
The panel power sequencing hardware tracks the stages of panel power
sequencing and signals when the panel is completely on or off. Instead
of blindly assuming the panel timings will work, poll the panel power
status register until it shows the correct values.
Signed-off-by: Keith Packard
---
dr
PCH eDP has many of the same needs as regular PCH DP connections,
including the DP_CTl bit settings, the TRANS_DP_CTL register.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_display.c |3 +-
drivers/gpu/drm/i915/intel_dp.c | 112 --
2 files
Found a couple of bare tabs in intel_dp.c
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_dp.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bf20a35..7ebeb01 100644
--- a/drivers/gpu
No persistent data was ever stored here, so link_status is instead
allocated on the stack as needed.
Signed-off-by: Keith Packard
---
drivers/gpu/drm/i915/intel_dp.c | 65 +-
1 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i9
Instead of going through the sequence just once, run through the whole
set up to 5 times to see if something can work. This isn't part of the
DP spec, but the BIOS seems to do it, and given that link training
failure is so bad, it seems reasonable to follow suit.
Signed-off-by: Keith Packard
---
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