Re: [Intel-gfx] [PATCH 6/8] drm/i915: change force wake order for GT read

On Tue, 22 Mar 2011 09:27:51 +0800, Zhenyu Wang wrote: > Just mean to follow the doc, it matches the sequence of RC6 enabling steps > from GT PM programming doc, not sure if it's strictly required. But as you point out, the docs do also outline the current method as well. ;-) Meanwhile a better

[Intel-gfx] next tidbits - use LLC on SNB

I had some fun playing around with Eric's patch to enable use of LLC on SandyBridge and built up a fair amount of complementary changes -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-

[Intel-gfx] [PATCH 04/15] drm/i915: Rename agp_type to cache_level

... to clarify just how we use it inside the driver. We still need to translate through agp_type for interface into the fake AGP driver. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c | 11 ++- drivers/gpu/drm/i915/i915_drv.h | 12 +--- driver

[Intel-gfx] [PATCH 07/15] drm/i915: Do not clflush snooped objects

Rely on the GPU snooping into the CPU cache for appropriately bound objects on MI_FLUSH. Or perhaps one day we will have a cache-coherent CPU/GPU package... Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --g

[Intel-gfx] [PATCH 10/15] drm/i915: Use kmap_atomic for shmem pread

We only hold the mapped pages for the duration of the memcpy, and never sleep with them, so we can safely use the cheaper atomic variants of kmap. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 16 1 files changed, 8 insertions(+), 8 deletions(-) diff --git

[Intel-gfx] [PATCH 12/15] drm/i915: s/addr & ~PAGE_MASK/offset_in_page(addr)/

Convert our open coded offset_in_page() to the common macro. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 21 ++--- 1 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index afb5

[Intel-gfx] [PATCH 15/15] drm/i915: Use the LLC mode on gen6 for everything but display.

From: Eric Anholt This provided a 10.4% +/- 1.5% (n=3) performance improvement on openarena on my laptop. We have more room to improve with doing LLC caching for display using GFDT, and in doing LLC+MLC caching, but this was an easy performance win and incremental improvement toward those two.

[Intel-gfx] [PATCH 14/15] drm/i915: Cleanup flush|invalidate domain tracking for set_to_gpu

After moving the write flushing into the move_to_ring, we can simplify the execbuffer flush by not having to compute inter-ring flushes. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 73 +++- 1 files changed, 17 insertions(+), 56 deletions

[Intel-gfx] [PATCH 13/15] drm/i915: Implement GTT variants of pread

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 184 -- 1 files changed, 174 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 37a8a29..8f60bc5 100644 --- a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 11/15] drm/i915: Use the CPU domain for snooped pwrites

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 96d4e64..afb5aaf 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 09/15] drm/i915: Refactor pwrite/pread to use single copy of get_user_pages

Replace the three nearly identical copies of the code with a single function. And take advantage of the opportunity to do some micro-optimisation: avoid the vmalloc if at all possible and also avoid dropping the lock unless we are forced to acquire the mm semaphore. Signed-off-by: Chris Wilson --

[Intel-gfx] [PATCH 08/15] drm/i915: Use the uncached domain for the display planes

From: Eric Anholt The simplest and common method for ensuring scanout coherency on all chipsets is to mark the scanout buffers as uncached (and for userspace to remember to flush the render cache every so often). We can improve upon this for later generations by marking scanout objects as GFDT a

[Intel-gfx] [PATCH 06/15] drm/i915: Add an interface to dynamically change the cache level

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h |6 +- drivers/gpu/drm/i915/i915_gem.c | 24 +++- drivers/gpu/drm/i915/i915_gem_gtt.c |8 +--- drivers/gpu/drm/i915/intel_ringbuffer.c |6 -- 4 files changed, 37 inser

[Intel-gfx] [PATCH 05/15] drm/i915: Mark the cursor and the overlay as being part of the display planes

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_display.c |2 +- drivers/gpu/drm/i915/intel_overlay.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3b0733d..f96620d 100644

[Intel-gfx] [PATCH 03/15] drm/i915: Track last read/write seqno independently

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_debugfs.c|5 ++- drivers/gpu/drm/i915/i915_drv.h| 17 +++-- drivers/gpu/drm/i915/i915_gem.c| 55 +++- drivers/gpu/drm/i915/i915_gem_execbuffer.c |1 - drivers/gpu/drm/

[Intel-gfx] [PATCH 02/15] drm/i915: Accurately track flushed domains

--- drivers/gpu/drm/i915/i915_drv.h| 10 +- drivers/gpu/drm/i915/i915_gem.c| 166 +--- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 33 +- drivers/gpu/drm/i915/intel_overlay.c |4 +- drivers/gpu/drm/i915/intel_ringbuffer.c| 6

[Intel-gfx] [PATCH 01/15] drm/i915: Enable use of GPU semaphores to sync page-flips on SNB

Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h|9 - drivers/gpu/drm/i915/i915_gem.c| 52 ++- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 43 +-- drivers/gpu/drm/i915/intel_display.c |6 +++-

[Intel-gfx] Pineview + libva

I'm building a HD network media player device and thought VAAPI was supposed to be supported on Pineview, am I wrong? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] Pineview + libva

On Tue, 2011-03-22 at 14:52 +, Steven Newbury wrote: > I'm building a HD network media player device and thought VAAPI was supposed > to be > supported on Pineview, am I wrong? To answer my own question somewhat, from the list here: http://en.wikipedia.org/wiki/Intel_GMA It's clear the Pine

Re: [Intel-gfx] Pineview + libva

On Tue, Mar 22, 2011 at 12:29 PM, Steven Newbury wrote: > On Tue, 2011-03-22 at 14:52 +, Steven Newbury wrote: >> I'm building a HD network media player device and thought VAAPI was supposed >> to be >> supported on Pineview, am I wrong? > > To answer my own question somewhat, from the list h

Re: [Intel-gfx] [PATCH 01/15] drm/i915: Enable use of GPU semaphores to sync page-flips on SNB

Might be nice to have the patch message mention that the bulk of this patch is simply renaming and moving i915_gem_execbuffer_sync_rings. In fact, doing this in two patches would make the actual change a whole lot easier to find. -- keith.pack...@intel.com pgpogFDNCbIgt.pgp Description: PGP si

Re: [Intel-gfx] [PATCH 02/15] drm/i915: Accurately track flushed domains

I'd love to see the API changes done in separate patches so they can be reviewed without being mixed in with the actual fixes. This patch conflates the changing of the sequence number management, ring synchronization, elimination of the file argument to i915_add_request with the changes in flush d

[Intel-gfx] [PATCH 0/4 rev2] Sandybridge suspend/resume fixes

I've done more testing with below patches, eliminated some in first patch set that doesn't affect suspend issue it seems. The test was done with one rev9 SNB on two boards DH67GD and DQ67SW with latest bios. And it both passed over 100 cycles of S3 testing. Without these, upstream kernel still han

[Intel-gfx] [PATCH 1/4] drm/i915: clock gating fix for gen5 and gen6

Some bits should only be set when enable FBC. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_reg.h |4 +++- drivers/gpu/drm/i915/intel_display.c | 27 ++- 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33

DSPARB is reserved on G33 and not available on Gen6. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_suspend.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 0521ecf..8d165c4

[Intel-gfx] [PATCH 3/4] drm/i915: save/restore MI_ARB_STATE only before gen6

MI_ARB_STATE address is not available on Gen6. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_suspend.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 8d165c4..bce24d8 100644

[Intel-gfx] [PATCH 4/4] drm/i915: move sandybridge RC6 enable in resume after ring initialization

Move RC6 enable after we reset rings for all regines, if e.g render ring is disabled when RC6 enable on Sandybridge, hw won't save render context image if any chance when enter RC6. Also match the order like we do in driver load. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_drv.c

Re: [Intel-gfx] [PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33

On Wed, 23 Mar 2011 10:21:07 +0800, Zhenyu Wang wrote: > DSPARB is reserved on G33 and not available on Gen6. Does this fix a reported problem? Or just spec compliance? -- keith.pack...@intel.com pgpSsTjeknBqr.pgp Description: PGP signature ___ Int

Re: [Intel-gfx] [PATCH 2/4] drm/i915: save/restore DSPARB only for chips before gen4 but not for G33

On 2011.03.23 12:03:41 +0900, Keith Packard wrote: > On Wed, 23 Mar 2011 10:21:07 +0800, Zhenyu Wang > wrote: > > > DSPARB is reserved on G33 and not available on Gen6. > > Does this fix a reported problem? Or just spec compliance? > I didn't verify if this one is really related, but save/res

Re: [Intel-gfx] [PATCH 0/4 rev2] Sandybridge suspend/resume fixes

On 2011/3/23 10:21, Zhenyu Wang wrote: I've done more testing with below patches, eliminated some in first patch set that doesn't affect suspend issue it seems. The test was done with one rev9 SNB on two boards DH67GD and DQ67SW with latest bios. And it both passed over 100 cycles of S3 testing.