> -Original Message-
> From: Govindapillai, Vinod
> Sent: Monday, April 7, 2025 5:35 PM
> To: Murthy, Arun R ; Deak, Imre
>
> Cc: intel...@lists.freedesktop.org; Kandpal, Suraj ;
> Nikula, Jani ; intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v9] drm/i915
Hi Arun,
While looking into another issue, noticed from the bspec 74379 that this is for
xe3+.
So the version checks should be based on "30" not "20"!
BR
Vinod
On Mon, 2025-03-03 at 09:55 +, Murthy, Arun R wrote:
> > Hi,
> >
> > I noticed a few issues in this patch (while fixing the other
On Mon, Mar 03, 2025 at 11:55:30AM +0200, Murthy, Arun R wrote:
> [...]
> > > +{
> > > + struct intel_encoder *encoder = connector->encoder;
> > > + struct intel_display *display = to_intel_display(encoder);
> > > + const struct drm_display_mode *adjusted_mode =
> > > +
> Hi,
>
> I noticed a few issues in this patch (while fixing the other ones reported),
> could
> you please check and follow up on the comments below? Thanks.
>
> On Wed, Jan 22, 2025 at 11:25:42AM +0530, Arun R Murthy wrote:
> > Mandate a minimum Hblank symbol cycle count between BlankingStart
Hi,
I noticed a few issues in this patch (while fixing the other ones
reported), could you please check and follow up on the comments
below? Thanks.
On Wed, Jan 22, 2025 at 11:25:42AM +0530, Arun R Murthy wrote:
> Mandate a minimum Hblank symbol cycle count between BlankingStart and
> BlankingEnd
On Wed, 22 Jan 2025, Arun R Murthy wrote:
> Mandate a minimum Hblank symbol cycle count between BlankingStart and
> BlankingEnd in 8b/10b MST and 128b/132b mode.
Mixed feelings. We're at v9. The patch has Reviewed-by. I'm asked to
ack. There's nothing incorrect with what's here as far as I can se
