> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, August 23, 2024 3:30 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment
hy, Arun R ; Manna, Animesh
> > ; jani.nik...@linux.intel.com
> > Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach
> > PC10
> >
> > On Fri, 2024-08-23 at 06:18 +, Kandpal, Suraj wrote:
> > >
> > >
> > > > -Original Message-
&g
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, August 23, 2024 12:51 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implme
Animesh
> > ; jani.nik...@linux.intel.com
> > Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach
> > PC10
> >
> > On Fri, 2024-08-23 at 04:54 +, Kandpal, Suraj wrote:
> > >
> > >
> > > > -Original Message-
>
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, August 23, 2024 10:54 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment
hy, Arun R ; Manna, Animesh
> > ; jani.nik...@linux.intel.com
> > Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach
> > PC10
> >
> > On Wed, 2024-06-19 at 10:07 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
>
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, August 22, 2024 2:16 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implme
On Wed, 2024-06-19 at 10:07 +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all
t: RE: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Suraj Kandpal
> > Sent: Wednesday, June 19, 2024 10:08 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Wednesday, June 19, 2024 10:08 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Murthy, Arun R
> ; Hogander, Jouni ;
> jani.nik...@linux.intel.com; Kandpal, Suraj
> Subject: [PATCH 2/2] drm/i915/
On Mon, 10 Jun 2024, "Kandpal, Suraj" wrote:
>> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>>
>> On Thu, 06 Jun 2024, Suraj Kandpal wrote:
>> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
>
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>
> On Thu, 06 Jun 2024, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 c
Hi Suraj,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.10-rc2 next-20240606]
[If your patch is applied to the wrong git tree, kindly drop us a not
Hi Suraj,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.10-rc2 next-20240606]
[If your patch is applied to the wrong git tree, kindly drop us
Hi Suraj,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-tip/drm-tip
linus/master v6.10-rc2 next-20240606]
[If your patch is applied to the wrong git tree, kindly drop us a not
On Thu, 06 Jun 2024, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have
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