On Mon, 2024-02-19 at 12:06 +0530, Suraj Kandpal wrote:
> If fixed refresh rate program the PKGC_LATENCY register
> with the highest latency from level 1 and above LP registers
> and program ADDED_WAKE_TIME = DSB execution time.
> else program PKGC_LATENCY with all 1's and ADDED_WAKE_TIME as 0.
> T
Hi Suraj,
+Ville - please comment if you see anything wrong with my explanation here
I think there could be a problem with the current logic and a possibility for
underrun. As per the
bspec we need to configure highest latency to soc.
As per this patch, skl_program_dpkgc_latency() is called fro
On Mon, 05 Feb 2024, "Kandpal, Suraj" wrote:
>> On Mon, 05 Feb 2024, Suraj Kandpal wrote:
>> > + if (wm_latency[i] == 0)
>> > + break;
>> > + else if (wm_latency[i] > max_value)
>> > + max_value = wm_latency[i];
>> > + }
>> > +
>> > + if (max_
Hi Suraj,
On Mon, 2024-02-05 at 13:31 +0530, Suraj Kandpal wrote:
> Program the PKGC_LATENCY register with the highest latency from
> level 1 and above LP registers else program with all 1's.
> This is used to improve package C residency by sending the highest
> latency tolerance requirement (LTR)
> Subject: Re: [PATCH 2/2] drm/i915/lnl: Program PKGC_LATENCY register
>
> On Mon, 05 Feb 2024, Suraj Kandpal wrote:
> > Program the PKGC_LATENCY register with the highest latency from level
> > 1 and above LP registers else program with all 1's.
> > This is use
On Mon, 05 Feb 2024, Suraj Kandpal wrote:
> Program the PKGC_LATENCY register with the highest latency from
> level 1 and above LP registers else program with all 1's.
> This is used to improve package C residency by sending the highest
> latency tolerance requirement (LTR) when the planes are don
> -Original Message-
> From: Kandpal, Suraj
> Sent: Thursday, February 1, 2024 2:22 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Kandpal,
> Suraj
> Subject: [PATCH 2/2] drm/i915/lnl: Program PKGC_LATENCY register
>
> Program the PKGC_LATENCY register with th
