Quoting Jani Nikula (2025-01-03 08:11:59-03:00)
>On Tue, 31 Dec 2024, Gustavo Sousa wrote:
>> Quoting Jani Nikula (2024-12-31 08:45:56-03:00)
>>>On Tue, 24 Dec 2024, Gustavo Sousa wrote:
>>>I understand you're following patterns from elsewhere in the driver. But
>>
>> Correct.
>>
>>>I've always w
On Tue, 31 Dec 2024, Gustavo Sousa wrote:
> Quoting Jani Nikula (2024-12-31 08:45:56-03:00)
>>On Tue, 24 Dec 2024, Gustavo Sousa wrote:
>>I understand you're following patterns from elsewhere in the driver. But
>
> Correct.
>
>>I've always wondered why we use a mixture of atomic state, global sta
On Tue, 2024-12-31 at 10:08 -0300, Gustavo Sousa wrote:
> Quoting Hogander, Jouni (2024-12-31 08:23:58-03:00)
> > On Tue, 2024-12-24 at 13:53 -0300, Gustavo Sousa wrote:
> > > The CMTG is a timing generator that runs in parallel with
> > > transcoders
> > > timing generators and can be used as a re
Quoting Jani Nikula (2024-12-31 08:45:56-03:00)
>On Tue, 24 Dec 2024, Gustavo Sousa wrote:
>> The CMTG is a timing generator that runs in parallel with transcoders
>> timing generators and can be used as a reference for synchronization.
>>
>> On PTL (display Xe3_LPD), we have observed that we are
Quoting Hogander, Jouni (2024-12-31 08:23:58-03:00)
>On Tue, 2024-12-24 at 13:53 -0300, Gustavo Sousa wrote:
>> The CMTG is a timing generator that runs in parallel with transcoders
>> timing generators and can be used as a reference for synchronization.
>>
>> On PTL (display Xe3_LPD), we have obs
On Tue, 24 Dec 2024, Gustavo Sousa wrote:
> The CMTG is a timing generator that runs in parallel with transcoders
> timing generators and can be used as a reference for synchronization.
>
> On PTL (display Xe3_LPD), we have observed that we are inheriting from
> GOP a display configuration with th
On Tue, 2024-12-24 at 13:53 -0300, Gustavo Sousa wrote:
> The CMTG is a timing generator that runs in parallel with transcoders
> timing generators and can be used as a reference for synchronization.
>
> On PTL (display Xe3_LPD), we have observed that we are inheriting
> from
> GOP a display confi
The CMTG is a timing generator that runs in parallel with transcoders
timing generators and can be used as a reference for synchronization.
On PTL (display Xe3_LPD), we have observed that we are inheriting from
GOP a display configuration with the CMTG enabled. Because our driver
doesn't currently
