Quoting Gustavo Sousa (2025-01-13 17:38:55-03:00)
>Pipe interrupt registers live in their respective pipes' power wells,
>which are below PG0. That means that they must also be tracked as
>registers that are powered-off during dynamic DC states.
>
>For that, we first convert the display IRQ code to
Pipe interrupt registers live in their respective pipes' power wells,
which are below PG0. That means that they must also be tracked as
registers that are powered-off during dynamic DC states.
For that, we first convert the display IRQ code to use display-specific
MMIO functions so that DMC wakelo
