> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Monday, December 18, 2023 7:50 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 5/7] drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2
> early transport
>
> Ther
There is a new register used to configure selective update area size
for early transport.
Configure PIPE_SRCSZ_ERLY_TPT using calculated selective update area
carried in crtc_state->su_area.
Bspec: 68927
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +
