> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, August 23, 2024 3:30 PM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment
hy, Arun R ; Manna, Animesh
> > ; jani.nik...@linux.intel.com
> > Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach
> > PC10
> >
> > On Fri, 2024-08-23 at 06:18 +, Kandpal, Suraj wrote:
> > >
> > >
> > > > -Original Message-
&g
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, August 23, 2024 12:51 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implme
Animesh
> > ; jani.nik...@linux.intel.com
> > Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach
> > PC10
> >
> > On Fri, 2024-08-23 at 04:54 +, Kandpal, Suraj wrote:
> > >
> > >
> > > > -Original Message-
>
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, August 23, 2024 10:54 AM
> To: Kandpal, Suraj ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment
hy, Arun R ; Manna, Animesh
> > ; jani.nik...@linux.intel.com
> > Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach
> > PC10
> >
> > On Wed, 2024-06-19 at 10:07 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
>
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, August 22, 2024 2:16 PM
> To: Kandpal, Suraj ; intel-
> g...@lists.freedesktop.org
> Cc: Murthy, Arun R ; Manna, Animesh
> ; jani.nik...@linux.intel.com
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implme
On Wed, 2024-06-19 at 10:07 +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all
: Manna, Animesh ; Murthy, Arun R
> > ; Hogander, Jouni
> ;
> > jani.nik...@linux.intel.com; Kandpal, Suraj
> > Subject: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>
> Nit: Typo in Implement
>
Wil fix.
> > To reach PC10 when PKG_C_LATENCY is configu
bject: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
Nit: Typo in Implement
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 c
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI
On Mon, 10 Jun 2024, "Kandpal, Suraj" wrote:
>> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>>
>> On Thu, 06 Jun 2024, Suraj Kandpal wrote:
>> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
>
> Subject: Re: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
>
> On Thu, 06 Jun 2024, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 c
ase: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:
https://lore.kernel.org/r/20240606082926.1816416-4-suraj.kandpal%40intel.com
patch subject: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
config: i386-buildonly-randconfig-002-20240607
(https://download.01.o
63351
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:
https://lore.kernel.org/r/20240606082926.1816416-4-suraj.kandpal%40intel.com
patch subject: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
config: x86_64-defconfig
(https://download.01.org/0day-ci/archiv
ase: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:
https://lore.kernel.org/r/20240606082926.1816416-4-suraj.kandpal%40intel.com
patch subject: [PATCH 2/2] drm/i915/psr: Implment WA to help reach PC10
config: microblaze-allmodconfig
(https://download.01.org/0day-ci/archiv
On Thu, 06 Jun 2024, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI
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