Re: [Intel-gfx] intel_pre_enable_dp

2013-09-29 Thread Jesse Barnes
On Mon, 30 Sep 2013 01:53:47 +0200 Andi Kleen wrote: > On Mon, Sep 30, 2013 at 01:48:13AM +0200, Andi Kleen wrote: > > > > Jesse, > > > > I was playing with a static analyzer and it flagged the following > > code of yours. > > > > Is the val = 0 directly after the register read correct and int

[Intel-gfx] intel_pre_enable_dp

2013-09-29 Thread Andi Kleen
Jesse, I was playing with a static analyzer and it flagged the following code of yours. Is the val = 0 directly after the register read correct and intended? commit 89b667f86a62a99a7b484a7e1b3f8f7a108a7dee Author: Jesse Barnes Date: Thu Apr 18 14:51:36 2013 -0700 drm/i915: update VLV PL

Re: [Intel-gfx] intel_pre_enable_dp

2013-09-29 Thread Andi Kleen
On Mon, Sep 30, 2013 at 01:48:13AM +0200, Andi Kleen wrote: > > Jesse, > > I was playing with a static analyzer and it flagged the following > code of yours. > > Is the val = 0 directly after the register read correct and intended? Also the same pattern is in other places, like vlv_pre_enable_d