On Wed, 18 May 2016, "Sanchez, AdolfoX" wrote:
> A customer of mine decided to work with a modified DP port with only
> two lanes and is facing issues. I guess modifying the suggested
> values might be useful at O.S leve, however I was wondering if
> modifyint the register that I mentioned earli
same for the pre-OS stage.
Best Regards,
Adolfo Sanchez
-Original Message-
From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
Sent: Wednesday, May 18, 2016 12:38 AM
To: Sanchez, AdolfoX ;
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] force DP lane count on Broadwell platform
On Wed, 18 May 2016, "Sanchez, AdolfoX" wrote:
> What PRM registers should be modified to force the source lanes to
> report 2 lanes maximum? Is it enough to modify the registers
> DP_TP_CTL and DDI_BUF_CTL, or should any other register be modified?
You should probably look at intel_ddi_init() i
Hello
What PRM registers should be modified to force the source lanes to report 2
lanes maximum?
Is it enough to modify the registers DP_TP_CTL and DDI_BUF_CTL, or should any
other register be modified?
Best Regards,
Adolfo Sanchez.
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