> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, August 7, 2017 7:13 PM
> To: Dong, Chuanxiao ; intel-
> g...@lists.freedesktop.org; Joonas Lahtinen
>
> Subject: RE: a potential dead loop in intel_lrc_irq_handler
>
> Quoting Dong, Chuanxiao (2017
Quoting Dong, Chuanxiao (2017-08-07 11:31:57)
> > -Original Message-
> > From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> > GPU reset -> clears CSB head/tail
> But the GPU reset will make CSB_head = 0 and CSB_tail = 7.
Experience says otherwise, but the issue of the delayed interrupt
> -Original Message-
> From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> Sent: Monday, August 7, 2017 5:56 PM
> To: Dong, Chuanxiao ; intel-
> g...@lists.freedesktop.org; Joonas Lahtinen
>
> Subject: Re: a potential dead loop in intel_lrc_irq_handler
>
> Quoting Dong, Chuanxiao (2017
Quoting Dong, Chuanxiao (2017-08-07 10:41:29)
> Hello,
>
> Found there might be a corner case for intel_lrc_irq_handler() in a dead
> loop, want to understand if this can be real or not.
>
> The scenario is like:
> 1. Write wedged to trigger a GPU reset;
This is dangerous full stop, but even w
Hello,
Found there might be a corner case for intel_lrc_irq_handler() in a dead loop,
want to understand if this can be real or not.
The scenario is like:
1. Write wedged to trigger a GPU reset;
2. meanwhile, there is one ongoing request in port[0], and its context switch
interrupt is generated
