On Thu, Nov 01, 2018 at 04:02:48PM -0700, Srivatsa, Anusha wrote:
>
>
> >-Original Message-
> >From: Navare, Manasi D
> >Sent: Thursday, November 1, 2018 3:31 PM
> >To: Srivatsa, Anusha
> >Cc: intel-gfx@lists.freedesktop.org; Jani Nikula
> >;
> >Ville Syrjala
> >Subject: Re: [v4 1/7] i
>-Original Message-
>From: Navare, Manasi D
>Sent: Thursday, November 1, 2018 3:31 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Jani Nikula ;
>Ville Syrjala
>Subject: Re: [v4 1/7] i915/dp/fec: Cache the FEC_CAPABLE DPCD register
>
>On Tue, Oct 30, 2018 at 05:45:11PM -0
On Tue, Oct 30, 2018 at 05:45:11PM -0700, Anusha Srivatsa wrote:
> Similar to DSC DPCD registers, let us cache
> FEC_CAPABLE register to avoid using stale
> values. With this we can avoid aux reads
> everytime and instead read the cached values.
>
> v2: Avoid using memset and array for a single
>
Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.
v2: Avoid using memset and array for a single
field. (Manasi,Jani)
v3:
Suggested-by: Jani Nikula
Cc: Jani Nikula
Cc: Vill
