> -Original Message-
> From: Lee, Shawn C
> Sent: Friday, July 23, 2021 12:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Chiou, Cooper
> ; Tseng, William ; Lee,
> Shawn C ; Jani Nikula
> Subject: [V3 5/7] drm/i915: Ge
VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.
v2:
- Check for dsc enable and slice count ==1 then allow to
double confir
