On 02/22/2014 01:37 AM, Jesse Barnes wrote:
On Fri, 24 Jan 2014 19:23:54 +0200
Imre Deak wrote:
On Fri, 2014-01-24 at 20:35 +0530, Naresh Kumar Kachhi wrote:
On 01/22/2014 06:53 PM, Imre Deak wrote:
On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
On Wed, Jan 22, 2014 at 05:34:17PM
On 01/24/2014 09:26 PM, Paulo Zanoni wrote:
2014/1/24 Naresh Kumar Kachhi :
On 01/22/2014 06:53 PM, Imre Deak wrote:
On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com
wrote:
From: Naresh Kumar Kachhi
With runtime
On Fri, 24 Jan 2014 19:23:54 +0200
Imre Deak wrote:
> On Fri, 2014-01-24 at 20:35 +0530, Naresh Kumar Kachhi wrote:
> > On 01/22/2014 06:53 PM, Imre Deak wrote:
> >
> > > On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
> > > > On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...
On Fri, 2014-01-24 at 20:35 +0530, Naresh Kumar Kachhi wrote:
> On 01/22/2014 06:53 PM, Imre Deak wrote:
>
> > On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
> > > On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com
> > > wrote:
> > > > From: Naresh Kumar Kachhi
> >
2014/1/24 Naresh Kumar Kachhi :
> On 01/22/2014 06:53 PM, Imre Deak wrote:
>
> On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
>
> On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com
> wrote:
>
> From: Naresh Kumar Kachhi
>
> With runtime PM enabled, we need to make sur
On 01/22/2014 06:53 PM, Imre Deak wrote:
On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com wrote:
From: Naresh Kumar Kachhi
With runtime PM enabled, we need to make sure that all HW access
are valid (i.e. Gfx is in
2014/1/22 :
> From: Naresh Kumar Kachhi
>
> With runtime PM enabled, we need to make sure that all HW access
> are valid (i.e. Gfx is in D0). Invalid accesses might end up in
> HW hangs. Ex. A hang is seen if display register is accessed on
> BYT while display power island is power gated.
>
> Th
On Wed, 2014-01-22 at 13:51 +0100, Daniel Vetter wrote:
> On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com wrote:
> > From: Naresh Kumar Kachhi
> >
> > With runtime PM enabled, we need to make sure that all HW access
> > are valid (i.e. Gfx is in D0). Invalid accesses migh
On Wed, Jan 22, 2014 at 05:34:17PM +0530, naresh.kumar.kac...@intel.com wrote:
> From: Naresh Kumar Kachhi
>
> With runtime PM enabled, we need to make sure that all HW access
> are valid (i.e. Gfx is in D0). Invalid accesses might end up in
> HW hangs. Ex. A hang is seen if display register is
From: Naresh Kumar Kachhi
With runtime PM enabled, we need to make sure that all HW access
are valid (i.e. Gfx is in D0). Invalid accesses might end up in
HW hangs. Ex. A hang is seen if display register is accessed on
BYT while display power island is power gated.
This patch is covering all th
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