On Wed, Feb 05, 2014 at 11:17:25AM -0800, Daniel Vetter wrote:
> On Wed, Feb 5, 2014 at 8:00 PM, Volkin, Bradley D
> wrote:
> > To test/merge, we'd have to change the series to take out the part where
> > patch 02/13 sets I915_DISPATCH_SECURE to avoid a BUG_ON() when
> > i915.enable_cmd_parser=1.
On Wed, Feb 5, 2014 at 8:00 PM, Volkin, Bradley D
wrote:
> To test/merge, we'd have to change the series to take out the part where
> patch 02/13 sets I915_DISPATCH_SECURE to avoid a BUG_ON() when
> i915.enable_cmd_parser=1.
> But yes, otherwise the parsing works and I think should be sufficient
On Wed, Feb 05, 2014 at 10:30:00AM -0800, Daniel Vetter wrote:
> On Wed, Feb 5, 2014 at 7:18 PM, Volkin, Bradley D
> wrote:
> > On Wed, Feb 05, 2014 at 02:28:29AM -0800, Chris Wilson wrote:
> >> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> >> > From: Brad Volkin
>
On Wed, Feb 5, 2014 at 7:18 PM, Volkin, Bradley D
wrote:
> On Wed, Feb 05, 2014 at 02:28:29AM -0800, Chris Wilson wrote:
>> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
>> > From: Brad Volkin
>> >
>> > Certain OpenGL features (e.g. transform feedback, performance mo
On Wed, Feb 05, 2014 at 02:28:29AM -0800, Chris Wilson wrote:
> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Certain OpenGL features (e.g. transform feedback, performance monitoring)
> > require userspace code to submit batches containi
On Wed, Feb 05, 2014 at 10:18:44AM -0800, Volkin, Bradley D wrote:
> On Wed, Feb 05, 2014 at 02:28:29AM -0800, Chris Wilson wrote:
> > On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > > From: Brad Volkin
> > >
> > > Certain OpenGL features (e.g. transform feedback,
On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> Certain OpenGL features (e.g. transform feedback, performance monitoring)
> require userspace code to submit batches containing commands such as
> MI_LOAD_REGISTER_IMM to access various registers.
On Wed, Dec 11, 2013 at 7:04 PM, Volkin, Bradley D
wrote:
>> We unfortunately don't really have tons of spare cycles from our QA team
>> for testing branches (pretty much none actually), so the usual approach is
>> to review and merge patches without first going through QA. If we pull in
>> your n
On Wed, Dec 11, 2013 at 01:54:40AM -0800, Daniel Vetter wrote:
> On Tue, Dec 10, 2013 at 04:58:18PM -0800, Volkin, Bradley D wrote:
> > So, I have a functioning kmap_atomic based parser using an sg_mapping_iter,
> > and in the
> > tests I'm running, it's worse than the vmap approach. This is still
On Tue, Dec 10, 2013 at 04:58:18PM -0800, Volkin, Bradley D wrote:
> So, I have a functioning kmap_atomic based parser using an sg_mapping_iter,
> and in the
> tests I'm running, it's worse than the vmap approach. This is still without
> the batch
> copy, but I think it's relevant anyhow. I haven
[snip]
On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > 2) Coherency. I've found two types of coherency issues when reading the
> > batch
> >buffer from the CPU during execbuffer2. Looking for help with both
> > issues.
> > i. First, the i-g-t test gem_cpu_reloc blits t
On Thu, Dec 5, 2013 at 9:47 PM, Volkin, Bradley D
wrote:
> On Tue, Nov 26, 2013 at 12:24:14PM -0800, Volkin, Bradley D wrote:
>> On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
>> > I think long-term we should even scan secure batches. We'd need to allow
>> > some registers which on
On Tue, Nov 26, 2013 at 12:24:14PM -0800, Volkin, Bradley D wrote:
> On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > I think long-term we should even scan secure batches. We'd need to allow
> > some registers which only the drm master (i.e. owner of the display
> > hardware) is a
On Thu, Dec 5, 2013 at 2:40 AM, Volkin, Bradley D
wrote:
>> > Ok, I'll look at the hw context code for buffer mgmt. For "purgeable",
>> > just via the
>> > madv field in the i915 gem object?
>>
>> Yeah, though I'd extract two tiny helpers (maybe shared with the madvise
>> ioctl) to set an object
On Wed, Dec 04, 2013 at 12:13:39AM -0800, Daniel Vetter wrote:
> On Tue, Nov 26, 2013 at 9:24 PM, Volkin, Bradley D
> wrote:
>
> [snip]
>
> > Which "state setup stuff" are you referring to? Something specific in i-g-t
> > or something
> > more general?
>
> The state setup 3D commands as oppos
On Wed, Dec 4, 2013 at 9:13 AM, Daniel Vetter wrote:
>> Ok, I'll look at the hw context code for buffer mgmt. For "purgeable", just
>> via the
>> madv field in the i915 gem object?
>
> Yeah, though I'd extract two tiny helpers (maybe shared with the madvise
> ioctl) to set an object to purgeable
On Tue, Nov 26, 2013 at 9:24 PM, Volkin, Bradley D
wrote:
[snip]
> Which "state setup stuff" are you referring to? Something specific in i-g-t
> or something
> more general?
The state setup 3D commands as opposed to doing actual rendering commands
(with 3D_PRIM). Just to have a bit more reali
On Wed, 2013-11-27 at 09:47 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 04:42:11PM +0800, Xiang, Haihao wrote:
> > On Wed, 2013-11-27 at 09:31 +0100, Daniel Vetter wrote:
> > > On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao
> > > wrote:
> > > >> So are these 2nd level batches construc
On Wed, 2013-11-27 at 09:47 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 04:42:11PM +0800, Xiang, Haihao wrote:
> > On Wed, 2013-11-27 at 09:31 +0100, Daniel Vetter wrote:
> > > On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao
> > > wrote:
> > > >> So are these 2nd level batches construct
On Wed, Nov 27, 2013 at 04:42:11PM +0800, Xiang, Haihao wrote:
> On Wed, 2013-11-27 at 09:31 +0100, Daniel Vetter wrote:
> > On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao
> > wrote:
> > >> So are these 2nd level batches constructed by the gpu in some cases? That
> > >> would be fairly horribly
On Wed, 2013-11-27 at 09:31 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao wrote:
> >> So are these 2nd level batches constructed by the gpu in some cases? That
> >> would be fairly horribly to take into account with the batch checker ...
> >
> > It is *not* the 2nd
On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao wrote:
>> So are these 2nd level batches constructed by the gpu in some cases? That
>> would be fairly horribly to take into account with the batch checker ...
>
> It is *not* the 2nd level batch buffer (bit 22 isn't set). Only batch
> buffer chain is
On Wed, 2013-11-27 at 09:10 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 09:32:32AM +0800, ykzhao wrote:
> > On Tue, 2013-11-26 at 13:24 -0700, Volkin, Bradley D wrote:
> > > On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > > > Hi Brad,
> > > >
> > > > On Tue, Nov 26, 2
On Wed, Nov 27, 2013 at 09:32:32AM +0800, ykzhao wrote:
> On Tue, 2013-11-26 at 13:24 -0700, Volkin, Bradley D wrote:
> > On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > > Hi Brad,
> > >
> > > On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com
> > > wrote:
> >
On Tue, 2013-11-26 at 13:24 -0700, Volkin, Bradley D wrote:
> On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > Hi Brad,
> >
> > On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > > From: Brad Volkin
> > >
> > > Certain OpenGL features (e.g. transfor
On Tue, 2013-11-26 at 20:35 +0100, Daniel Vetter wrote:
> Hi Brad,
>
> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Certain OpenGL features (e.g. transform feedback, performance monitoring)
> > require userspace code to submit batches
On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> Hi Brad,
>
> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Certain OpenGL features (e.g. transform feedback, performance monitoring)
> > require userspace code to submit b
Hi Brad,
On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> From: Brad Volkin
>
> Certain OpenGL features (e.g. transform feedback, performance monitoring)
> require userspace code to submit batches containing commands such as
> MI_LOAD_REGISTER_IMM to access various r
From: Brad Volkin
Certain OpenGL features (e.g. transform feedback, performance monitoring)
require userspace code to submit batches containing commands such as
MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
generations of the hardware will noop these commands in "unsecure"
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