Re: [Intel-gfx] [PATCH v8 10/17] pwm: crc: Fix period changes not having any effect

On Sun, Aug 30, 2020 at 02:57:46PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > The BACKLIGHT_EN register at address 0x51 really controls a separate > output-only GPIO

[Intel-gfx] [PATCH v8 10/17] pwm: crc: Fix period changes not having any effect

The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register The BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is earmarked to be used as output connected to the backlight-enable