On Tue, Sep 29, 2020 at 11:42:22PM -0700, Lucas De Marchi wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
> mapping as in ICL/TGL.
>
> The values for VBT seem wrong in BSpec. For the current
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
>From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.
The values for VBT seem wrong in BSpec. For the current boards we
actually have a 1:1 mapping.
BSpec: 49311, 49945, 20124
Cc: A
