Re: [Intel-gfx] [PATCH v5 2/2] drm/i915/skl: Add DC5 Trigger Sequence

2015-05-04 Thread Daniel Vetter
On Fri, Apr 17, 2015 at 07:46:16PM +0530, Animesh Manna wrote: > From: Suketu Shah > > Add triggers as per expectations mentioned in gen9_enable_dc5 > and gen9_disable_dc5 patch. > > Also call POSTING_READ for every write to a register to ensure that > its written immediately. > > v1: Remove PO

Re: [Intel-gfx] [PATCH v5 2/2] drm/i915/skl: Add DC5 Trigger Sequence

2015-04-30 Thread Imre Deak
On pe, 2015-04-17 at 19:46 +0530, Animesh Manna wrote: > From: Suketu Shah > > Add triggers as per expectations mentioned in gen9_enable_dc5 > and gen9_disable_dc5 patch. > > Also call POSTING_READ for every write to a register to ensure that > its written immediately. > > v1: Remove POSTING_RE

[Intel-gfx] [PATCH v5 2/2] drm/i915/skl: Add DC5 Trigger Sequence

2015-04-17 Thread Animesh Manna
From: Suketu Shah Add triggers as per expectations mentioned in gen9_enable_dc5 and gen9_disable_dc5 patch. Also call POSTING_READ for every write to a register to ensure that its written immediately. v1: Remove POSTING_READ calls as they've already been added in previous patches. v2: Rebase t