Sent: Thursday, July 19, 2018 9:51 PM
>>>> To: Chauhan, Madhav
>>>> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
>>>> Zanoni, Paulo R ; Vivi, Rodrigo
>>>>
>>>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>&g
i ;
Zanoni, Paulo R ; Vivi, Rodrigo
Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
TA_TIMING_PARAM registers
On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
This patch programs D-PHY timing parameters for the bus turn around
flow(in escape clocks) only if dsi link
ani ;
>> Zanoni, Paulo R ; Vivi, Rodrigo
>>
>> Subject: Re: [Intel-gfx] [PATCH v5 09/13] drm/i915/icl: Program
>> TA_TIMING_PARAM registers
>>
>> On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
>> > This patch programs D-PHY timing parameters
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Thursday, July 19, 2018 9:51 PM
> To: Chauhan, Madhav
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani ;
> Zanoni, Paulo R ; Vivi, Rodrigo
>
> Subject: Re: [Intel-gfx] [
On Tue, Jul 10, 2018 at 03:10:10PM +0530, Madhav Chauhan wrote:
> This patch programs D-PHY timing parameters for the
> bus turn around flow(in escape clocks) only if dsi link
> frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
> identical register DSI_TA_TIMING_PARAM (inside DSI
> Controller
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
Signed-off-by: Madhav Chauhan
---
drivers/gpu
