Re: [Intel-gfx] [PATCH v5] drm/i915: Added write-enable pte bit support

2014-06-17 Thread Daniel Vetter
On Tue, Jun 17, 2014 at 10:59:42AM +0530, akash.g...@intel.com wrote: > From: Akash Goel > > This adds support for a write-enable bit in the entry of GTT. > This is handled via a read-only flag in the GEM buffer object which > is then used to see how to set the bit when writing the GTT entries. >

[Intel-gfx] [PATCH v5] drm/i915: Added write-enable pte bit support

2014-06-16 Thread akash . goel
From: Akash Goel This adds support for a write-enable bit in the entry of GTT. This is handled via a read-only flag in the GEM buffer object which is then used to see how to set the bit when writing the GTT entries. Currently by default the Batch buffer & Ring buffers are marked as read only. v2