Re: [Intel-gfx] [PATCH v5] drm/i915/psr: Account for sink CRC raciness on some panels

2017-08-16 Thread Jim Bride
On Tue, Aug 15, 2017 at 04:41:52PM -0700, Rodrigo Vivi wrote: > On Tue, Aug 15, 2017 at 9:58 AM, Jim Bride wrote: > > On Wed, Aug 09, 2017 at 01:40:00PM -0700, Jim Bride wrote: > >> According to the eDP spec, when the count field in TEST_SINK_MISC > >> increments then the six bytes of sink CRC inf

Re: [Intel-gfx] [PATCH v5] drm/i915/psr: Account for sink CRC raciness on some panels

2017-08-15 Thread Rodrigo Vivi
On Tue, Aug 15, 2017 at 9:58 AM, Jim Bride wrote: > On Wed, Aug 09, 2017 at 01:40:00PM -0700, Jim Bride wrote: >> According to the eDP spec, when the count field in TEST_SINK_MISC >> increments then the six bytes of sink CRC information in the DPCD >> should be valid. Unfortunately, this doesn't

[Intel-gfx] [PATCH v5] drm/i915/psr: Account for sink CRC raciness on some panels

2017-08-09 Thread Jim Bride
According to the eDP spec, when the count field in TEST_SINK_MISC increments then the six bytes of sink CRC information in the DPCD should be valid. Unfortunately, this doesn't seem to be the case on some panels, and as a result we get some incorrect and inconsistent values from the sink CRC DPCD