On Tue, Jun 07, 2016 at 10:02:35AM +0300, Jani Nikula wrote:
> On Mon, 06 Jun 2016, Lyude Paul wrote:
> > On Mon, 2016-06-06 at 14:30 +0300, Ville Syrjälä wrote:
> >> On Thu, May 26, 2016 at 09:54:56AM +0200, Daniel Vetter wrote:
> >> >
> >> > Queued for -next, thanks for the patch.
> >> Looks li
On Mon, 06 Jun 2016, Lyude Paul wrote:
> On Mon, 2016-06-06 at 14:30 +0300, Ville Syrjälä wrote:
>> On Thu, May 26, 2016 at 09:54:56AM +0200, Daniel Vetter wrote:
>> >
>> > Queued for -next, thanks for the patch.
>> Looks like this one broke one of the ILKs in CI.
>>
>> [ 13.100979] [drm:ironl
On Mon, 2016-06-06 at 14:30 +0300, Ville Syrjälä wrote:
> On Thu, May 26, 2016 at 09:54:56AM +0200, Daniel Vetter wrote:
> >
> > On Wed, May 25, 2016 at 02:11:02PM -0400, Lyude wrote:
> > >
> > > Thanks to Ville Syrjälä for pointing me towards the cause of this issue.
> > >
> > > Unfortunately o
On Thu, May 26, 2016 at 09:54:56AM +0200, Daniel Vetter wrote:
> On Wed, May 25, 2016 at 02:11:02PM -0400, Lyude wrote:
> > Thanks to Ville Syrjälä for pointing me towards the cause of this issue.
> >
> > Unfortunately one of the sideaffects of having the refclk for a DPLL set
> > to SSC is that a
On Wed, May 25, 2016 at 02:11:02PM -0400, Lyude wrote:
> Thanks to Ville Syrjälä for pointing me towards the cause of this issue.
>
> Unfortunately one of the sideaffects of having the refclk for a DPLL set
> to SSC is that as long as it's set to SSC, the GPU will prevent us from
> powering down a
Thanks to Ville Syrjälä for pointing me towards the cause of this issue.
Unfortunately one of the sideaffects of having the refclk for a DPLL set
to SSC is that as long as it's set to SSC, the GPU will prevent us from
powering down any of the pipes or transcoders using it. A couple of
BIOSes enabl
