Re: [Intel-gfx] [PATCH v3 2/2] drm/i915: Sanitycheck PCI BARs

2022-08-10 Thread Jani Nikula
On Fri, 05 Aug 2022, "Piorkowski, Piotr" wrote: > From: Piotr PiĆ³rkowski > > For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 > (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. > Let's add functions to check if BARs are set, and that it have > a size greater than 0

[Intel-gfx] [PATCH v3 2/2] drm/i915: Sanitycheck PCI BARs

2022-08-05 Thread Piorkowski, Piotr
From: Piotr PiĆ³rkowski For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. Let's add functions to check if BARs are set, and that it have a size greater than 0. In case GTTMMADDR BAR, let's validate at the beginning of