actually just ignore my last msg... alternate between gmail and mutt
confused me...
On Wed, Nov 6, 2013 at 1:02 PM, wrote:
> From: Ville Syrjälä
>
> As per the SNB and HSW PM guides, we should enable FBC render/blitter
> tracking only during batches targetting the front buffer.
>
> On SNB we
ops, I just noticed that by mistake I replied the v1-series
but I actually looked to v2 seires... Sorry about that
On Wed, Nov 20, 2013 at 3:17 PM, Chris Wilson wrote:
> On Wed, Nov 20, 2013 at 02:55:57PM -0800, Rodrigo Vivi wrote:
>> On Wed, Nov 06, 2013 at 11:02:21PM +0200, ville.syrj...@li
On Wed, Nov 20, 2013 at 02:55:57PM -0800, Rodrigo Vivi wrote:
> On Wed, Nov 06, 2013 at 11:02:21PM +0200, ville.syrj...@linux.intel.com wrote:
> > static void
> > +i915_gem_execbuffer_mark_fbc_dirty(struct intel_ring_buffer *ring,
> > + struct list_head *vmas)
> > +{
>
On Wed, Nov 06, 2013 at 11:02:21PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> As per the SNB and HSW PM guides, we should enable FBC render/blitter
> tracking only during batches targetting the front buffer.
You improved things a lot here, but I'm just not convinced th
From: Ville Syrjälä
As per the SNB and HSW PM guides, we should enable FBC render/blitter
tracking only during batches targetting the front buffer.
On SNB we must also update the FBC render tracking address whenever it
changes. And since the register in question is stored in the context,
we need
