On ma, 2015-04-13 at 11:50 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Purpose of this tracking is to know when to flush the cache between
> the CPU and the non-coherent display engine. Prior to:
>
>commit 121920faf2ccce9aa66a7e2588415c9647b66104
>Author: Tvrtko Ursulin
>
From: Tvrtko Ursulin
Purpose of this tracking is to know when to flush the cache between
the CPU and the non-coherent display engine. Prior to:
commit 121920faf2ccce9aa66a7e2588415c9647b66104
Author: Tvrtko Ursulin
Date: Mon Mar 23 11:10:37 2015 +
drm/i915/skl: Query disp
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6104
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -4 272/272
On Tue, Mar 31, 2015 at 04:10:05PM +0300, Joonas Lahtinen wrote:
> On ti, 2015-03-31 at 13:55 +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin
> >
> > Purpose of this tracking is to know when to flush the cache between
> > the CPU and the non-coherent display engine. Prior to:
> >
> >co
Hi,
On 03/31/2015 02:10 PM, Joonas Lahtinen wrote:
On ti, 2015-03-31 at 13:55 +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Purpose of this tracking is to know when to flush the cache between
the CPU and the non-coherent display engine. Prior to:
commit 121920faf2ccce9aa66a7e2588415
On ti, 2015-03-31 at 13:55 +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Purpose of this tracking is to know when to flush the cache between
> the CPU and the non-coherent display engine. Prior to:
>
>commit 121920faf2ccce9aa66a7e2588415c9647b66104
>Author: Tvrtko Ursulin
>
From: Tvrtko Ursulin
Purpose of this tracking is to know when to flush the cache between
the CPU and the non-coherent display engine. Prior to:
commit 121920faf2ccce9aa66a7e2588415c9647b66104
Author: Tvrtko Ursulin
Date: Mon Mar 23 11:10:37 2015 +
drm/i915/skl: Query disp
