Re: [Intel-gfx] [PATCH v3] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

2016-03-20 Thread Arun Siluvery
On 16/03/2016 16:13, tim.g...@intel.com wrote: From: Tim Gore This allows writes to EU flow control registers. Together with SIP code from the user-mode driver this resolves a hang seen in some pre-emption scenarios. Note that this patch is just the kernel mode part of this workaround. v2. Oop

[Intel-gfx] [PATCH v3] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

2016-03-18 Thread tim . gore
From: Tim Gore This allows writes to EU flow control registers. Together with SIP code from the user-mode driver this resolves a hang seen in some pre-emption scenarios. Note that this patch is just the kernel mode part of this workaround. v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.