On Thursday 16 April 2015 12:09 AM, Ville Syrjälä wrote:
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Vil
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6201
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Wed, Apr 15, 2015 at 07:41:39PM +0530, deepa...@linux.intel.com wrote:
> From: Deepak S
>
> This WA is avoid problem between shadow vs wake FIFO unload
> problem during CPD/RC6 transactions on CHV.
>
> v2: Define individual bits GTFIFOCTL (Ville)
>
> v3: move WA to uncore_early_sanitize (vil
From: Deepak S
This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.
v2: Define individual bits GTFIFOCTL (Ville)
v3: move WA to uncore_early_sanitize (ville)
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu
