Re: [Intel-gfx] [PATCH v2 8/9] drm/i915: expose eu topology to userspace

2017-11-02 Thread Lionel Landwerlin
On 02/11/17 16:35, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-02 16:29:48) +/* Query various aspects of the topology of the GPU. Below is a list of the + * currently supported queries. The motivation of this more detailed query + * mechanism is to expose asynmetric properties of the

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915: expose eu topology to userspace

2017-11-02 Thread Lionel Landwerlin
On 02/11/17 16:35, Chris Wilson wrote: Quoting Lionel Landwerlin (2017-11-02 16:29:48) +/* Query various aspects of the topology of the GPU. Below is a list of the + * currently supported queries. The motivation of this more detailed query + * mechanism is to expose asynmetric properties of the

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915: expose eu topology to userspace

2017-11-02 Thread Chris Wilson
Quoting Lionel Landwerlin (2017-11-02 16:29:48) > +/* Query various aspects of the topology of the GPU. Below is a list of the > + * currently supported queries. The motivation of this more detailed query > + * mechanism is to expose asynmetric properties of the GPU. Starting with > CNL, > + * sli

[Intel-gfx] [PATCH v2 8/9] drm/i915: expose eu topology to userspace

2017-11-02 Thread Lionel Landwerlin
With the introduction of asymetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts of the GPU with the OA unit, because counters nee