On Friday 15 November 2013 01:57 PM, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase. The ULPS entry/exit
sequne
On Wednesday 20 November 2013 07:09 AM, Shobhit Kumar wrote:
On Friday 15 November 2013 02:25 PM, Daniel Vetter wrote:
On Fri, Nov 15, 2013 at 10:27:25AM +0200, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_ena
On Friday 15 November 2013 02:25 PM, Daniel Vetter wrote:
On Fri, Nov 15, 2013 at 10:27:25AM +0200, Jani Nikula wrote:
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also
On Fri, Nov 15, 2013 at 10:27:25AM +0200, Jani Nikula wrote:
> On Sat, 09 Nov 2013, Shobhit Kumar wrote:
> > Basically ULPS handling during enable/disable has been moved to
> > pre_enable and post_disable phases. PLL and panel power disable
> > also has been moved to post_disable phase. The ULPS e
On Sat, 09 Nov 2013, Shobhit Kumar wrote:
> Basically ULPS handling during enable/disable has been moved to
> pre_enable and post_disable phases. PLL and panel power disable
> also has been moved to post_disable phase. The ULPS entry/exit
> sequneces as suggested by HW team is as follows -
>
> Dur
Basically ULPS handling during enable/disable has been moved to
pre_enable and post_disable phases. PLL and panel power disable
also has been moved to post_disable phase. The ULPS entry/exit
sequneces as suggested by HW team is as follows -
During enable time -
set DEVICE_READY --> Clear DEVICE_RE
