Re: [Intel-gfx] [PATCH v2 34/50] drm/i915/dg2: Skip shared DPLL handling

On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote: > DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded > within the PHY. > > Bspec: 54032 > Bspec: 54034 Reviewed-by: José Roberto de Souza > Cc: Lucas De Marchi > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/d

[Intel-gfx] [PATCH v2 34/50] drm/i915/dg2: Skip shared DPLL handling

DG2 has no shared DPLL's or DDI clock muxing. The Port PLL is embedded within the PHY. Bspec: 54032 Bspec: 54034 Cc: Lucas De Marchi Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 - 2 files ch