On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The docs say that the trickle feed disable bit is present (for primary
> planes only, not video sprites) on CTG, and that it must be set
> for ELK. Just set it for all g4x chipsets.
>
> v2: D
On Tue, May 21, 2013 at 02:52:24PM +0200, Daniel Vetter wrote:
> On Tue, May 21, 2013 at 2:35 PM, Ville Syrjälä
> wrote:
> > On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrj...@linux.intel.com
> > wrote:
> >> From: Ville Syrjälä
> >>
> >> The docs say that the trickle feed disable bit is pre
On Tue, May 21, 2013 at 2:35 PM, Ville Syrjälä
wrote:
> On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrj...@linux.intel.com wrote:
>> From: Ville Syrjälä
>>
>> The docs say that the trickle feed disable bit is present (for primary
>> planes only, not video sprites) on CTG, and that it must be
On Tue, May 21, 2013 at 03:28:32PM +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The docs say that the trickle feed disable bit is present (for primary
> planes only, not video sprites) on CTG, and that it must be set
> for ELK. Just set it for all g4x chipsets.
>
> v2: D
From: Ville Syrjälä
The docs say that the trickle feed disable bit is present (for primary
planes only, not video sprites) on CTG, and that it must be set
for ELK. Just set it for all g4x chipsets.
v2: Do it in init_clock_gating too
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_
