On Wed, Jun 09, 2021 at 04:35:57PM +0200, Thomas Hellström wrote:
>
> On 6/9/21 3:08 PM, Thomas Hellström wrote:
> >
> > On 6/9/21 2:20 PM, Matthew Auld wrote:
> > > On 09/06/2021 13:16, Thomas Hellström wrote:
> > > >
> > > > On 6/9/21 1:48 PM, Daniel Vetter wrote:
> > > > > On Wed, Jun 09, 202
On 6/9/21 3:08 PM, Thomas Hellström wrote:
On 6/9/21 2:20 PM, Matthew Auld wrote:
On 09/06/2021 13:16, Thomas Hellström wrote:
On 6/9/21 1:48 PM, Daniel Vetter wrote:
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
A couple of patches from Chris which implement pipelined m
On 6/9/21 2:20 PM, Matthew Auld wrote:
On 09/06/2021 13:16, Thomas Hellström wrote:
On 6/9/21 1:48 PM, Daniel Vetter wrote:
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing th
On 09/06/2021 13:16, Thomas Hellström wrote:
On 6/9/21 1:48 PM, Daniel Vetter wrote:
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing the PTEs in place before performing the
act
On 6/9/21 1:48 PM, Daniel Vetter wrote:
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing the PTEs in place before performing the
actual blit.
Some ww utilities mainly for the ac
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
> A couple of patches from Chris which implement pipelined migration and
> clears by atomically writing the PTEs in place before performing the
> actual blit.
>
> Some ww utilities mainly for the accompanying selftests added by Thom
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing the PTEs in place before performing the
actual blit.
Some ww utilities mainly for the accompanying selftests added by Thomas,
as well as modified the above patches for ww locking- and lmem support.