On Wed, 22 Nov 2023 13:48:21 +0100, Christian Brauner wrote:
> Hey everyone,
>
> This simplifies the eventfd_signal() and eventfd_signal_mask() helpers
> significantly. They can be made void and not take any unnecessary
> arguments.
>
> I've added a few more simplifications based on Sean's sugges
On 11/22/23 5:48 AM, Christian Brauner wrote:
> Hey everyone,
>
> This simplifies the eventfd_signal() and eventfd_signal_mask() helpers
> significantly. They can be made void and not take any unnecessary
> arguments.
>
> I've added a few more simplifications based on Sean's suggestion.
>
> Sign
Hey everyone,
This simplifies the eventfd_signal() and eventfd_signal_mask() helpers
significantly. They can be made void and not take any unnecessary
arguments.
I've added a few more simplifications based on Sean's suggestion.
Signed-off-by: Christian Brauner
Changes in v2:
- further simplify
From: John Harrison
Enable Wa_14019159160 and Wa_16019325821 for MTL
RCS/CCS workarounds for MTL.
v2: Fix bug in WA KLV implementation (offset not being reset to start
of list). Add better comment to prep patch about how KLVs can be added.
Add a module parameter override and disable the w/a by
Hi all,
This the series from Jonathan:
[PATCH v12 0/4] Apply Wa_16018031267 / Wa_16018063123
taken over by me.
Changes in this version are described in the patches, in short:
- use real memory as WABB destination,
- address CI compains - do not decrease vm.total,
- minor reordering.
Regards
And
Convert i915's fbdev code to struct drm_client. Replaces the current
ad-hoc integration. The conversion includes a number of cleanups.
As with most other driver's fbdev emulation, fbdev in i915 is now
just another DRM client that runs after the DRM device has been
registered. This allows to remove
Up until now all dp hdcp specific function derived the aux
from dig_port which gave the aux of the primary port but with
DPMST when a MST hub comes into picture the monitor becomes remote
and what we need is a corresponding aux which is also remote.
These set of patches aim to fix up just that.
--
SDP split config for DP-MST
v2: Style changes and patch splits (Jani Nikula)
Vinod Govindapillai (4):
drm/i915/display: remove redundant parameter from sdp split update
drm/i915/display: combine has_audio check for DP and DP-MST
drm/i915/display: combine DP audio compute config steps
drm/
While 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
fixes the problem for lane reset logic, there are also more parts of the
implementation that need to take owned PHY lanes into consideration.
This series provides fixes for such places. The changes to the logic
have been teste
Currently i915 dirtyfb ioctl is not taking dma fences into
account. This works with features like FBC, PSR, DRRS because our gem
code is triggering flush again when rendering completes. We are
targeting in getting rid of frontbuffer tracking code: Flusing hook
from gem code will be removed as well.
Hi,
Here are four patches with some clean-ups in the code that handles the
max lane count of Type-C connections.
This is done mostly in preparation for a new way to read the pin
assignments and lane count in future devices.
In v2:
* Fix some rebasing damage.
Please review.
Cheers,
Luca.
L
Hi,
as there are new hardware directives, we need a little adaptation
for the AUX invalidation sequence.
In this version we support all the engines affected by this
change.
The stable backport has some challenges because the original
patch that this series fixes has had more changes in between.
On 6/26/23 11:14, Thomas Hellström wrote:
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
A couple of ttm fixes for issues that either were hit while developing the
xe driver or, for the resource leak patches, discovered during code
inspection.
v2:
-
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
A couple of ttm fixes for issues that either were hit while developing the
xe driver or, for the resource leak patches, discovered during code
inspection.
v2:
- Avoid a goto in patch 3 (Andi Shyti)
- Add som
We are preparing for Xe driver. Binary objects will have differing
implementation in Xe driver. Due this we want to remove direct
accesses to i915_gem_object members and leave details to binary object
implementation.
v2: desribe i915_ggtt_clear_scanout function parameter
Cc: Jani Nikula
Cc: Rodr
From: John Harrison
The GuC error capture list creation was including Gen8 registers on Xe
platforms. While fixing that, it was noticed that there were other
issues. The platform naming was wrong, the naming of lists was
misleading, the steered register code was duplicated and steered
registers w
Hi,
On 19.04.2023 00:04, Radhakrishna Sripada wrote:
This series adds 2 MTL WA's and 2 patches to fix re-use
"DC off" power wells.
v2:
Haridhar Kalvala (1):
drm/i915/mtl: WA to clear RDOP clock gating
Madhumitha Tolakanahalli Pradeep (1):
drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
On platforms where the GSC is part of GT, it needs to communicate with
CSME for some of its operations. However, there is no direct HW
communication channel, so the i915 and mei drivers must carry the
messages back and forth between the 2 units. The protocol is fully
described in the i915 patch tha
This series adds 2 MTL WA's and 2 patches to fix re-use
"DC off" power wells.
v2:
Haridhar Kalvala (1):
drm/i915/mtl: WA to clear RDOP clock gating
Madhumitha Tolakanahalli Pradeep (1):
drm/i915/mtl: Extend Wa_22011802037 to MTL A-step
Matt Roper (2):
drm/i915: Use separate "DC off" power
From: Ville Syrjälä
Remainder of the eDP HPD check series, now rebased on top
of MTL HPD stuff.
Ville Syrjälä (4):
drm/i915: Introduce _hotplug_mask()
drm/i915: Introduce intel_hpd_enable_detection()
drm/i915: Check HPD live state during eDP probe
drm/i915: Reuse _hotplug_mask() in .hpd_
On Fri, 2023-01-27 at 19:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> A bunch of stuff related to vblank length/start.
>
> v2: Fix inactive pipe handling
> Fix SAGV handling
> Fix some typos
For the whole set:
Reviewed-by: Jouni Högander
>
> Ville Syrjälä (4):
> drm/i91
This is v2 of [1] fixing DG2 platforms without display, addressing the
review comments from Jani and fixing one related issue noticed by the
bug reporter.
[1] https://patchwork.freedesktop.org/series/113711/
Cc: Jani Nikula
Imre Deak (4):
drm/i915: Fix system suspend without fbdev being initi
From: Ville Syrjälä
A bunch of stuff related to vblank length/start.
v2: Fix inactive pipe handling
Fix SAGV handling
Fix some typos
Ville Syrjälä (4):
drm/i915/vrr: Fix "window2" handling
drm/i915/psr: Fix the delayed vblank w/a
drm/i915: Extract skl_wm_latency()
drm/i915: Reje
On Wed, Nov 30, 2022 at 05:05:31PM -0800, Umesh Nerlige Ramappa wrote:
Enable OA for MTL by adding 32-bit OA format support and relevant fixes.
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20221129010522.994524-1-umesh.nerlige.rama...@intel.com
https://patchwork.freedesktop.org/series/1115
Enable OA for MTL by adding 32-bit OA format support and relevant fixes.
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20221129010522.994524-1-umesh.nerlige.rama...@intel.com
Umesh Nerlige Ramappa (4):
drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs
drm/i915/mtl: Add Wa_1401
Enable OA for MTL by adding 32-bit OA format support and relevant fixes.
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Ramappa (4):
drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs
drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch
drm/i915/mtl: Update O
Hi,
This series adds guards around vma's but setting a pages at the
beginning and at the end that work as padding.
The first user of the vma guard are scanout objects which don't
need anymore to add scratch to all the unused ggtt's and speeding
up up considerably the boot and resume by several hu
On Wed, 09 Nov 2022, Lucas De Marchi wrote:
> On Wed, Nov 09, 2022 at 05:35:18PM +0200, Jani Nikula wrote:
>>The remaining patches from [1], rebased.
>>
>>I also realized this conflicts with what Lucas is doing so I'd like to
>>get feedback.
>
> if you are talking about
> https://patchwork.freedes
On Wed, Nov 09, 2022 at 05:35:18PM +0200, Jani Nikula wrote:
The remaining patches from [1], rebased.
I also realized this conflicts with what Lucas is doing so I'd like to
get feedback.
if you are talking about
https://patchwork.freedesktop.org/series/109606/, then that series
pretty much st
The remaining patches from [1], rebased.
I also realized this conflicts with what Lucas is doing so I'd like to
get feedback.
[1] https://patchwork.freedesktop.org/series/110404/
Jani Nikula (4):
drm/i915/reg: move masked field helpers to i915_reg_defs.h
drm/i915/reg: move pick even and pick
From: Ville Syrjälä
Some cleanups for checking whether the crtc was flagged for
modesets/fastsets/color update.
v2: Handle {connectors,active}_changed, and convert one
more fastset check in fbc code
Ville Syrjälä (4):
drm/i915: Introduce intel_crtc_needs_fastset()
drm/i915: Remove some
On Thu, 20 Oct 2022, Imre Deak wrote:
> This is v2 of [1] addressing the review comments from Jani.
Did not do detailed review,
Acked-by: Jani Nikula
>
> [1]
> https://lore.kernel.org/intel-gfx/y1barftah%2fl+x...@ideak-desk.fi.intel.com/T/#t
>
> Cc: Jani Nikula
> Cc: Ville Syrjälä
>
> Imre
This is v2 of [1] addressing the review comments from Jani.
[1]
https://lore.kernel.org/intel-gfx/y1barftah%2fl+x...@ideak-desk.fi.intel.com/T/#t
Cc: Jani Nikula
Cc: Ville Syrjälä
Imre Deak (4):
drm/i915/tgl+: Add locking around DKL PHY register accesses
drm/i915: Rename intel_tc_phy_regs
From: "Kandpal, Suraj"
This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
---v2
-adding fields missed for vdsc_
Hi Andrzej,
On Thu, Oct 06, 2022 at 06:31:56PM +0200, Andrzej Hajda wrote:
> This patchset should not modify behaviour of the code (except patch 3).
> It just replaces sequence of uncore read/modify/write with single call.
> Moreover it replaces nested pointers with alias if there is one.
> All pa
This patchset should not modify behaviour of the code (except patch 3).
It just replaces sequence of uncore read/modify/write with single call.
Moreover it replaces nested pointers with alias if there is one.
All patches except 3rd, were generated using coccinelle (quite ugly)
and adjusted in some
On Fri, 16 Sep 2022, Ankit Nautiyal wrote:
> Fix issues in HFVSDB parsing for DSC support.
> Also minor refactoring in Logging.
>
> Split from original patch into a new series.
> https://patchwork.freedesktop.org/patch/495193/
>
> v2: Minor styling fixes.
Thanks for the patches, pushed to drm-mis
On Mon, 26 Sep 2022, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Start to clean up the mess around DPLL IDs a bit by removing
> the nasty assumption that the index of the DPLL in the
> arrays matches its ID. Fortunately we did have a WARN
> i nthere to cathc mistakes, but better to not has suc
From: Ville Syrjälä
Chang DRRS debugfs to be per-crtc/connector.
v2: for ci to actually run the drrs tests...
Test-with: 20220929032642.16556-1-ville.syrj...@linux.intel.com
Ville Syrjälä (4):
drm/i915: Move DRRS debugfs next to the implementation
drm/i915: Make the DRRS debugfs contents m
From: Ville Syrjälä
Start to clean up the mess around DPLL IDs a bit by removing
the nasty assumption that the index of the DPLL in the
arrays matches its ID. Fortunately we did have a WARN
i nthere to cathc mistakes, but better to not has such
silly assumptions i nthe first place.
There's still
Fix issues in HFVSDB parsing for DSC support.
Also minor refactoring in Logging.
Split from original patch into a new series.
https://patchwork.freedesktop.org/patch/495193/
v2: Minor styling fixes.
Ankit Nautiyal (4):
drm/edid: Fix minimum bpc supported with DSC1.2 for HDMI sink
drm/edid: S
Now that MTL is going to start providing two GTs, there are a few more
places in the driver that need to iterate over each GT instead of
operating directly on gt0. Also some more deliberate cleanup is needed,
in cases where we fail GT/engine initialization after the first GT has
been fully setup.
On Tue, Sep 13, 2022 at 12:56:49PM +0200, Thomas Zimmermann wrote:
>
>
> Am 13.09.22 um 12:54 schrieb Thomas Zimmermann:
> > Hi
> >
> > Am 13.09.22 um 12:47 schrieb Hogander, Jouni:
> >> On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
> >>> On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni
Am 13.09.22 um 12:54 schrieb Thomas Zimmermann:
Hi
Am 13.09.22 um 12:47 schrieb Hogander, Jouni:
On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
Currently damage clips handling is broken for planes when using big
frameb
Hi
Am 13.09.22 um 12:47 schrieb Hogander, Jouni:
On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
Currently damage clips handling is broken for planes when using big
framebuffer + offset in case kms driver adjusts drm_plane
On Tue, 2022-09-13 at 12:04 +0300, Ville Syrjälä wrote:
> On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
> > Currently damage clips handling is broken for planes when using big
> > framebuffer + offset in case kms driver adjusts drm_plane_state.src
> > coords. This is because damag
On Tue, Aug 23, 2022 at 02:29:16PM +0300, Jouni Högander wrote:
> Currently damage clips handling is broken for planes when using big
> framebuffer + offset in case kms driver adjusts drm_plane_state.src
> coords. This is because damage clips are using coords relative to
> original coords from user
Currently damage clips handling is broken for planes when using big
framebuffer + offset in case kms driver adjusts drm_plane_state.src
coords. This is because damage clips are using coords relative to
original coords from user-space.
This patchset is fixing this by using original
coords from user
From: Ville Syrjälä
Eliminate unnecessary includes from drm_crtc.h to avoid
pointless rebuilds of the entire universe when touching
some random header.
v2: Half the series already merged
Fix up a few allmodconfig fails not spotted earlier
Split the vmwgfx change into its own patch to mak
On newer platforms (starting DG2 G10 B-step and G11 A-step), ownership of
HuC loading and authentication has been moved from the GuC to the GSC, with
both actions being performed via a single PXP command.
Given that the mei code has not fully landed yet (see [1]), we can't
implement the new load me
I did some light testing with our anvil (Vulkan) and iris (OpenGL)
Mesa drivers after applying these patches on top of drm-tip tagged
intel/CI_DRM_11574. All the unit tests that I tried passed. I also ran
the gl_manhattan31 benchmark which used the compute engine for iris
compute shader ops.
Serie
Now that the necessary GuC-based hardware workarounds have landed, we're
finally ready to actually enable compute engines for use by userspace.
All of the "under-the-hood" heavy lifting already landed a while back in
other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE
to the ua
From: Ville Syrjälä
Start reordering when we do the clock/dpll calculations
during the atomic check. The eventual goals are:
- back feed the actually calculated clock into the crtc state
so that stuff that depends on it (eg. watermarks) will be
calculated based on the actual hardware state we
Flat-CCS eviction enhancements
v2: Correcting the memory residency requirement for flat-ccs capability
[Thomas]
Ramalingam C (4):
drm/i915/gt: GEM_BUG_ON unexpected NULL at scatterlist walking
drm/i915/gt: optimize the ccs_sz calculation per chunk
drm/i915/gt: Document the eviction of t
Few bug fixes for lrc selftest.
Resending the reviewed patches for CI feedback.
Chris Wilson (4):
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Always cancel semaphore on error
drm/i915/selft
This is v2 of [1] amending the authorship and commit log in patch 4 and
adding the r-bs, acks. Resending for CI as well for retesting on drm-tip
where the dependency patchset [2] is now also part of the drm-intel-next
branch.
[1] https://patchwork.freedesktop.org/series/102147/
[2] https://patchwo
Reviewed-by: Nirmoy Das for the series as well.
On 01/03/2022 22:53, Ramalingam C wrote:
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support
the 3D and media compression formats.
The memory required for the CCS of the
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support
the 3D and media compression formats.
The memory required for the CCS of the entire local memory is
1/256 of the local memory size. So before the kernel
boot, the requir
This is John/Rodrigo's 2 patches with some minor changes, and I added
2 patches.
"drm/i915/uapi: Add query for hwconfig blob" was changed:
* Rename DRM_I915_QUERY_HWCONFIG_TABLE to DRM_I915_QUERY_HWCONFIG_BLOB
as requested by Joonas.
* Reword commit message
* I added Acked-by to this patc
Misc fixes and refactoring in HDMI2.1 PCON helper functions.
V2:
Addressed review comments from Jani.
Splitted the drm_helper addition and usage in separate patches.
Ankit Nautiyal (4):
drm/i915/hdmi: Fix the definition of intel_hdmi_dsc_get_bpp
drm/edid: Add helper to get max FRL rate for an
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert ad
This series continues support for 64K pages for discrete cards.
It supersedes the 64K patches from
https://patchwork.freedesktop.org/series/95686/#rev4
Changes since that series:
- set min alignment for DG2 to 2MB in i915_address_space_init
- replace coloring with simpler 2MB VA alignment for lme
From: Ville Syrjälä
A bit more prep work towards multiple FBC instances.
Main changes since v1:
- More intel_ namespace
- per-crtc debugfs files
- a few other review comments addressed
Cc: Jani Nikula
Ville Syrjälä (4):
drm/i91
Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.
These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.
Note: The patches are not tested due
Hi,
On 10/7/21 11:54 AM, Hans de Goede wrote:
> Hi,
>
> On 10/5/21 10:26 PM, Lyude Paul wrote:
>> On Sat, 2021-10-02 at 11:14 +0200, Hans de Goede wrote:
>>> Hi Lyude,
>>>
>>> On 10/2/21 12:53 AM, Lyude Paul wrote:
When I originally moved all of the VESA backlight code in i915 into DRM
Hi,
On 10/5/21 10:26 PM, Lyude Paul wrote:
> On Sat, 2021-10-02 at 11:14 +0200, Hans de Goede wrote:
>> Hi Lyude,
>>
>> On 10/2/21 12:53 AM, Lyude Paul wrote:
>>> When I originally moved all of the VESA backlight code in i915 into DRM
>>> helpers, one of the things I didn't have the hardware or ti
On Sat, 2021-10-02 at 11:14 +0200, Hans de Goede wrote:
> Hi Lyude,
>
> On 10/2/21 12:53 AM, Lyude Paul wrote:
> > When I originally moved all of the VESA backlight code in i915 into DRM
> > helpers, one of the things I didn't have the hardware or time for
> > testing was machines that used a comb
Hi Lyude,
On 10/2/21 12:53 AM, Lyude Paul wrote:
> When I originally moved all of the VESA backlight code in i915 into DRM
> helpers, one of the things I didn't have the hardware or time for
> testing was machines that used a combination of PWM and DPCD in order to
> control their backlights. This
When I originally moved all of the VESA backlight code in i915 into DRM
helpers, one of the things I didn't have the hardware or time for
testing was machines that used a combination of PWM and DPCD in order to
control their backlights. This has since then caused some breakages and
resulted in us d
From: Ville Syrjälä
The way we calculate the CFB stride/size is kind of a mess, and
I'm not sure if we're even allocating enough stolen memory always.
Let's make it all more straightforward, and add some new related
workarounds as well.
Some of the earlier patches already got merged, and for the
From: Ville Syrjälä
I ran into some kind of fail with VT-d superpage on Geminlake igfx,
so without any better ideas let's just disable it.
Additionally Skylake/Broxton igfx have known issues with VT-d
superpage as well, so let's disable it there as well. This should
let us re-enable frame buffer
Early implementation of moving system memory for discrete cards over to
TTM. We first add the notion of objects being migratable under the object
lock to i915 gem, and add some asserts to verify that objects are either
locked or pinned when the placement is checked by the gem code.
Patch 2 and 3 d
Hi all,
I finally figured out why CI is unhappy on some machines, we've lost WC
mode on the vgem side!
Test-with: 20210527140732.5762-1-daniel.vet...@ffwll.ch
Cheers, Daniel
Daniel Vetter (4):
drm/gem-shmem-helper: Export drm_gem_shmem_funcs
drm/shmem-helper: Switch to vmf_insert_pfn
drm/
First and second patches should be straightforward. Third patch is a
simplification for gen9+ since we are not supposed to check the straps
anymore and rely on VBT. Finally last patch may or may not make sense:
I'm trying to hide these hacks in intel_bios.c so we have a clean init
sequence.
Lucas
Now that we have a common set of function for general lrc management,
the only remaining dependency the guc submission code has towards the
execlists submission is the engine setup. This series gets rid of that
by copying the required execlists setup function in the GuC submission
file; the copied
This is the v2 version after testing DP with some rough
changes in kms_content_protection IGT in order to test stream
encryption with multiple streams.
DP MST link authentication, stream encryption and link integrity
check has been tested with this series on TGL platform.
Anshuman Gupta (4):
drm
On 2020-05-23 02:41, Chris Wilson wrote:
Quoting John Hubbard (2020-05-22 06:19:27)
The purpose of posting this series is to launch a test in the
intel-gfx-ci tree. (The patches have already been merged into Andrew's
linux-mm tree.)
This applies to today's linux.git (note the base-commit tag at
The purpose of posting this series is to launch a test in the
intel-gfx-ci tree. (The patches have already been merged into Andrew's
linux-mm tree.)
This applies to today's linux.git (note the base-commit tag at the
bottom).
Changes since V1:
* Fixed a bug in the refactoring patch: added FOLL_FA
Quoting John Hubbard (2020-05-22 06:19:27)
> The purpose of posting this series is to launch a test in the
> intel-gfx-ci tree. (The patches have already been merged into Andrew's
> linux-mm tree.)
>
> This applies to today's linux.git (note the base-commit tag at the
> bottom).
>
> Changes since
Instead of spreading multiple conditionals across the uC code
to find out current mode of uC operation, start using predefined
set of function pointers that reflect that mode.
v2: rebased, using macro to generate ops helpers
Michal Wajdeczko (4):
drm/i915/uc: Add ops to intel_uc
drm/i915/uc:
On 11/22/19 6:56 PM, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> My earlier fixes for drm_rect + div-by-zero fix + some
> selftests that Daniel requested.
>
> Cc: Maarten Lankhorst
> Cc: Benjamin Gaignard
> Cc: Daniel Vetter
Thanks to have handle this.
Reviewed-by: Benjamin Gaignard
>
>
From: Ville Syrjälä
My earlier fixes for drm_rect + div-by-zero fix + some
selftests that Daniel requested.
Cc: Maarten Lankhorst
Cc: Benjamin Gaignard
Cc: Daniel Vetter
Ville Syrjälä (4):
drm/rect: Avoid division by zero
drm/rect: Keep the scaled clip bounded
drm/rect: Keep the clippe
v2: rename + don't care about undocumented values <0
changes in IGT to stop using enable_guc modparam to detect
guc_submission mode will follow shortly
Michal Wajdeczko (4):
drm/i915/uc: Rename intel_uc_is_using* into intel_uc_supports*
drm/i915/uc: Consider enable_guc modparam during fw sele
v2:
- Fix sparse warning
- Do not try to make header self-contained
- Fix coding style while moving code
Anusha Srivatsa (1):
drm/i915: Add modular FIA
Lucas De Marchi (3):
drm/i915: make new intel_tc.c use uncore accessors
drm/i915: fix include order in intel_tc.*
drm/i915: move in
This patch series enables programming of Multi-segmented-gamma
palette for ICL.
Shashank Sharma (3):
drm/i915: Change gamma/degamma_lut_size data type to u32
drm/i915: Rename ivb_load_lut_10_max
drm/i915/icl: Add Multi-segmented gamma support
Uma Shankar (1):
drm/i915/icl: Add register de
In case of tiled displays, each tile is sent across a separate CRTC and a
separate port/connector connected to the monitor. In this case we need to make
sure that the timings across these transcoders/ports are synchronized else
the two tile displays can be off.
Transcoder Port Sync is a transcoder
Quoting Jani Nikula (2019-02-27 11:01:58)
> On Thu, 17 Jan 2019, Chris Wilson wrote:
> > Quoting Jani Nikula (2019-01-17 12:13:59)
> >> The v1 [1] kind of died down because the FIELD_PREP() build-time checks
> >> were lost as it didn't evaluate to integer constant expression. I looked
> >> at this
On Thu, 17 Jan 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-01-17 12:13:59)
>> The v1 [1] kind of died down because the FIELD_PREP() build-time checks
>> were lost as it didn't evaluate to integer constant expression. I looked
>> at this again, and managed to include the checks in the loc
This fixes the extra issues I discovered upstream after the introduction
of my rework of the atomic VCPI helpers that occur during
suspend/resume.
This time around, we use a slightly different but much less complicated
approach for fixing said issues.
Cc: Daniel Vetter
Lyude Paul (4):
drm/dp_
Some PLL reworks on ICL. Patches are more or less independent of each
other, but touch the same part of the code.
v2 of https://patchwork.freedesktop.org/series/55378/
Changes: typos, commit messages and checkpatch fix. I'm dropping the
last commit as we don't really need it right now and when/if
Quoting Jani Nikula (2019-01-17 12:13:59)
> The v1 [1] kind of died down because the FIELD_PREP() build-time checks
> were lost as it didn't evaluate to integer constant expression. I looked
> at this again, and managed to include the checks in the local copy by
> using BUILD_BUG_ON_ZERO() instead.
The v1 [1] kind of died down because the FIELD_PREP() build-time checks
were lost as it didn't evaluate to integer constant expression. I looked
at this again, and managed to include the checks in the local copy by
using BUILD_BUG_ON_ZERO() instead.
On the naming bikeshedding department, I noticed
This is v2 of [1]. The changes in v2:
- Use VBT for detecting legacy ports. There was already a flag for this
in VBT, I just missed it. Thanks for Siva for pointing that out. With
that we have a detection that works all the time for DP ports as well.
- Remove a redundant special casing of legac
Hi Tvrtko,
> On Wed, Nov 7, 2018 at 4:08 PM Tvrtko Ursulin
> wrote:
>
>
> On 06/11/2018 04:13, Ankit Navik wrote:
> > drm/i915: Context aware user agnostic EU/Slice/Sub-slice control
> > within kernel
> >
> > Current GPU configuration code for i915 does not allow us to change
> > EU/Slice/Sub-
On 06/11/2018 04:13, Ankit Navik wrote:
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel
Current GPU configuration code for i915 does not allow us to change
EU/Slice/Sub-slice configuration dynamically. Its done only once while context
is created.
While particular
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel
Current GPU configuration code for i915 does not allow us to change
EU/Slice/Sub-slice configuration dynamically. Its done only once while context
is created.
While particular graphics application is running, if we exa
This patchset does some cleaning up of the atomic VCPI helpers for MST,
and converts nouveau over to using them. I would have included amdgpu in
this patch as well, but at the moment moving them over to the atomic
helpers is nontrivial.
Cc: Daniel Vetter
Lyude Paul (4):
drm/dp_mst: Add some at
These patches enable packed format YUV422-Y210, Y212 and Y216
for 10, 12 and 16 bit respectively for ICL.
For user space component IGT:WIP
v2: addressed review comments of mahesh and alexandru
hdr handling of these 64 bit pixel format not inscope
of this series
Vidya Srinivas (4):
drm
This is the next version of my patch series for teaching DRM how to
automatically create debugfs nodes for drivers with MST topologies. This
was originally intended just for nouveau, but has since been expanded to
all DRM drivers.
Changes since previous version:
- Fix documentation error that got
v2: Rebase and add better comment for Pxxx formats into drm_fourcc.h
These patches enable P010, P012 and P016 formats for GLK and CNL.
These formats are similar to NV12 extending from 8 bits per channel
to 10, 12 and 16 bits per channel.
For user space components there is in IGT kms_available_mod
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