On Mon, Feb 13, 2017 at 02:54:01PM +, Robert Bragg wrote:
> On Mon, Feb 13, 2017 at 2:28 PM, Ville Syrjälä
> wrote:
> > On Sun, Feb 12, 2017 at 01:32:52PM +, Robert Bragg wrote:
> >> This workaround for BDW was incomplete as it also requires EUTC clock
> >> gating to be disabled via UCGCTL
On Mon, Feb 13, 2017 at 2:28 PM, Ville Syrjälä
wrote:
> On Sun, Feb 12, 2017 at 01:32:52PM +, Robert Bragg wrote:
>> This workaround for BDW was incomplete as it also requires EUTC clock
>> gating to be disabled via UCGCTL1.
>>
>> v2: read modify write UCGTL1 in broadwell_init_clock_gating (Vi
On Sun, Feb 12, 2017 at 01:32:52PM +, Robert Bragg wrote:
> This workaround for BDW was incomplete as it also requires EUTC clock
> gating to be disabled via UCGCTL1.
>
> v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)
>
> Signed-off-by: Robert Bragg
> Cc: Ville Syrjälä
This workaround for BDW was incomplete as it also requires EUTC clock
gating to be disabled via UCGCTL1.
v2: read modify write UCGTL1 in broadwell_init_clock_gating (Ville)
Signed-off-by: Robert Bragg
Cc: Ville Syrjälä
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drivers/gpu/drm/i915/intel_pm.c | 8
drivers/gpu/drm/i
