On Tue, Jun 02, 2015 at 12:37:13PM +0300, Imre Deak wrote:
> On ma, 2015-06-01 at 12:01 -0700, Rodrigo Vivi wrote:
> > On Mon, Jun 1, 2015 at 12:32 AM, Imre Deak wrote:
> > > The divider value to convert from CZ clock rate to ms needs a +1
> > > adjustment on VLV just like on CHV. This matches bot
On ma, 2015-06-01 at 12:01 -0700, Rodrigo Vivi wrote:
> On Mon, Jun 1, 2015 at 12:32 AM, Imre Deak wrote:
> > The divider value to convert from CZ clock rate to ms needs a +1
> > adjustment on VLV just like on CHV. This matches both the spec and
> > the accuracy test by pm_rc6_residency.
> >
> > v
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6512
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, Jun 1, 2015 at 12:32 AM, Imre Deak wrote:
> The divider value to convert from CZ clock rate to ms needs a +1
> adjustment on VLV just like on CHV. This matches both the spec and
> the accuracy test by pm_rc6_residency.
>
> v2:
> - simplify logic checking for the CHV 320MHz special case (Ro
The divider value to convert from CZ clock rate to ms needs a +1
adjustment on VLV just like on CHV. This matches both the spec and
the accuracy test by pm_rc6_residency.
v2:
- simplify logic checking for the CHV 320MHz special case (Rodrigo)
Testcase: igt/pm_rc6_residency
Signed-off-by: Imre Dea
