Re: [Intel-gfx] [PATCH 78/89] drm/i915/skl: Flush the WM configuration

2014-09-19 Thread Ville Syrjälä
On Thu, Sep 04, 2014 at 12:27:44PM +0100, Damien Lespiau wrote: > When we write new values for the DDB allocation and WM parameters, we now > need to trigger the double buffer update for the pipe to take the new > configuration into account. > > As the DDB is a global resource shared between plane

[Intel-gfx] [PATCH 78/89] drm/i915/skl: Flush the WM configuration

2014-09-04 Thread Damien Lespiau
When we write new values for the DDB allocation and WM parameters, we now need to trigger the double buffer update for the pipe to take the new configuration into account. As the DDB is a global resource shared between planes, enabling or disabling one plane will result in changes for all planes t