Re: [Intel-gfx] [PATCH 63/89] drm/i915/skl: Define shared DPLLs for Skylake

2014-10-01 Thread M, Satheeshakrishna
On 9/23/2014 7:58 PM, Paulo Zanoni wrote: 2014-09-04 8:27 GMT-03:00 Damien Lespiau: From: Satheeshakrishna M On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll framework allows us to share those DPLLs among DDIs when possible. The most tricky part is to provide a DPLL sta

Re: [Intel-gfx] [PATCH 63/89] drm/i915/skl: Define shared DPLLs for Skylake

2014-09-23 Thread Paulo Zanoni
2014-09-04 8:27 GMT-03:00 Damien Lespiau : > From: Satheeshakrishna M > > On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll > framework allows us to share those DPLLs among DDIs when possible. > > The most tricky part is to provide a DPLL state that can be easily > compared.

[Intel-gfx] [PATCH 63/89] drm/i915/skl: Define shared DPLLs for Skylake

2014-09-04 Thread Damien Lespiau
From: Satheeshakrishna M On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll framework allows us to share those DPLLs among DDIs when possible. The most tricky part is to provide a DPLL state that can be easily compared. DPLL_CRTL1 is shared by all the DPLLs, 6 bits each. Th