Re: [Intel-gfx] [PATCH 6.3/9] drm/i915: merge HSW and SNB PM irq handlers

2013-08-20 Thread Daniel Vetter
On Thu, Aug 15, 2013 at 11:51:32AM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does > and also processes the 2 additional VEBOX bits. So merge those > functions and wrap the VEBOX bits on a HAS_VEBOX check. This > check isn

[Intel-gfx] [PATCH 6.3/9] drm/i915: merge HSW and SNB PM irq handlers

2013-08-15 Thread Paulo Zanoni
From: Paulo Zanoni Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does and also processes the 2 additional VEBOX bits. So merge those functions and wrap the VEBOX bits on a HAS_VEBOX check. This check isn't really necessary since the bits are reserved on SNB/IVB/VLV, but it's a

Re: [Intel-gfx] [PATCH 6.3/9] drm/i915: merge HSW and SNB PM irq handlers

2013-08-14 Thread Ben Widawsky
On Fri, Aug 09, 2013 at 05:04:37PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does > and also processes the 2 additional VEBOX bits. So merge those > functions and wrap the VEBOX bits on an IS_HASWELL check. This HSW > che

[Intel-gfx] [PATCH 6.3/9] drm/i915: merge HSW and SNB PM irq handlers

2013-08-09 Thread Paulo Zanoni
From: Paulo Zanoni Because hsw_pm_irq_handler does exactly what gen6_rps_irq_handler does and also processes the 2 additional VEBOX bits. So merge those functions and wrap the VEBOX bits on an IS_HASWELL check. This HSW check isn't really necessary since the bits are reserved on SNB/IVB/VLV, but