Re: [Intel-gfx] [PATCH 5/5] drm/i915: Force sync command ordering (Gen6+)

2011-10-12 Thread Daniel Vetter
On Tue, Oct 11, 2011 at 09:43:53PM -0700, Ben Widawsky wrote: > The docs say this is required for Gen7, and since the bit was added for > Gen6, we are also setting it there pit pf paranoia. Particularly as > Chris points out, if PIPE_CONTROL counts as a 3d state packet. > > This was found through

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Force sync command ordering (Gen6+)

2011-10-12 Thread Ben Widawsky
On Oct 11, 2011, at 9:43 PM, Ben Widawsky wrote: > The docs say this is required for Gen7, and since the bit was added for > Gen6, we are also setting it there pit pf paranoia. Particularly as > Chris points out, if PIPE_CONTROL counts as a 3d state packet. > > This was found through doc inspec

[Intel-gfx] [PATCH 5/5] drm/i915: Force sync command ordering (Gen6+)

2011-10-11 Thread Ben Widawsky
The docs say this is required for Gen7, and since the bit was added for Gen6, we are also setting it there pit pf paranoia. Particularly as Chris points out, if PIPE_CONTROL counts as a 3d state packet. This was found through doc inspection by Ken and applies to Gen6+; It is currently hanging Dan