On Thu, 3 Nov 2011 12:57:08 -0700, Jesse Barnes
wrote:
> Modulo what we already discussed on irc about the PP_READY bit, and the
Right, the PP_READY bit requires that everything needed for PCH eDP be
running, even when you're using a CPU connected eDP panel, and so it's
not actually useful.
>
On Tue, 1 Nov 2011 23:20:27 -0700
Keith Packard wrote:
> The panel power sequencing hardware tracks the stages of panel power
> sequencing and signals when the panel is completely on or off. Instead
> of blindly assuming the panel timings will work, poll the panel power
> status register until i
On Wed, 2 Nov 2011 09:23:10 -0700, Jesse Barnes
wrote:
> Note that PP_READY will incorrectly depend on some other register
> values, so in some configs the panel will happily power up even if
> PP_READY isn't set yet...
Here's the new version of that chunk:
@@ -906,32 +905,56 @@ intel_dp_mode_
On Wed, 2 Nov 2011 09:23:10 -0700, Jesse Barnes
wrote:
> Note that PP_READY will incorrectly depend on some other register
> values, so in some configs the panel will happily power up even if
> PP_READY isn't set yet...
Yeah, I'd like to understand why PP_READY isn't getting set; we should
have
On Wed, 02 Nov 2011 00:31:40 -0700
Keith Packard wrote:
> On Tue, 1 Nov 2011 23:20:27 -0700, Keith Packard wrote:
>
> > -static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
> > +#define IDLE_ON_MASK (PP_ON | PP_READY | PP_SEQUENCE_MASK |
> > 0 | PP
On Tue, 1 Nov 2011 23:20:27 -0700, Keith Packard wrote:
> -static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
> +#define IDLE_ON_MASK (PP_ON | PP_READY | PP_SEQUENCE_MASK | 0
> | PP_SEQUENCE_STATE_MASK)
> +#define IDLE_ON_VALUE(PP_ON | PP_READY |
The panel power sequencing hardware tracks the stages of panel power
sequencing and signals when the panel is completely on or off. Instead
of blindly assuming the panel timings will work, poll the panel power
status register until it shows the correct values.
Signed-off-by: Keith Packard
---
dr
