Re: [Intel-gfx] [PATCH 4/4] drm/i915: don't set the FBC plane select bits on HSW+

2015-06-14 Thread shuang . he
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 6573 -Summary- Platform Delta drm-intel-nightly Series Applied PNV

[Intel-gfx] [PATCH 4/4] drm/i915: don't set the FBC plane select bits on HSW+

2015-06-12 Thread Paulo Zanoni
From: Paulo Zanoni This commit is just to make the intentions explicit: on HSW+ these bits are MBZ, but since we only support plane A and the macro evaluates to zero when plane A is the parameter, we're not fixing any bug. v2: - Remove useless extra blank like (Chris). - Init dpfc_ctl in anoth

Re: [Intel-gfx] [PATCH 4/4] drm/i915: don't set the FBC plane select bits on HSW+

2015-06-12 Thread Chris Wilson
On Thu, Jun 11, 2015 at 04:02:27PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > This commit is just to make the intentions explicit: on HSW+ these > bits are MBZ, but since we only support plane A and the macro > evaluates to zero when plane A is the parameter, we're not fixing any > bug.

[Intel-gfx] [PATCH 4/4] drm/i915: don't set the FBC plane select bits on HSW+

2015-06-11 Thread Paulo Zanoni
From: Paulo Zanoni This commit is just to make the intentions explicit: on HSW+ these bits are MBZ, but since we only support plane A and the macro evaluates to zero when plane A is the parameter, we're not fixing any bug. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 7 ++