Re: [Intel-gfx] [PATCH 32/33] drm/i915/guc: Implement GuC priority management

2022-06-07 Thread John Harrison
On 6/7/2022 06:58, Tvrtko Ursulin wrote: A blast from the past.. On 27/07/2021 01:23, Matthew Brost wrote: Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0  -> GuC low le

Re: [Intel-gfx] [PATCH 32/33] drm/i915/guc: Implement GuC priority management

2022-06-07 Thread Tvrtko Ursulin
A blast from the past.. On 27/07/2021 01:23, Matthew Brost wrote: Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> Gu

[Intel-gfx] [PATCH 32/33] drm/i915/guc: Implement GuC priority management

2021-07-26 Thread Matthew Brost
Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i915 level < INT_MAX-> GuC high level(1) i9

Re: [Intel-gfx] [PATCH 32/33] drm/i915/guc: Implement GuC priority management

2021-07-23 Thread Daniele Ceraolo Spurio
On 7/22/2021 4:54 PM, Matthew Brost wrote: Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i91

[Intel-gfx] [PATCH 32/33] drm/i915/guc: Implement GuC priority management

2021-07-22 Thread Matthew Brost
Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i915 level < INT_MAX-> GuC high level(1) i9