On Mon, May 06, 2013 at 07:37:35PM -0300, Rodrigo Vivi wrote:
> Display register 42020h bit 9 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: RMW to preserve other bits (by Ville)
> v3: Fix from Ville: sed &/| at RMW
Looks like you went a bit too far with
Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: RMW to preserve other bits (by Ville)
v3: Fix from Ville: sed &/| at RMW
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm
On Thu, Apr 25, 2013 at 02:15:22PM -0300, Rodrigo Vivi wrote:
> Display register 42020h bit 9 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> v2: RMW to preserve other bits (by Ville)
>
> Cc: Ville Syrjälä
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/
Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
v2: RMW to preserve other bits (by Ville)
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++
1 file changed, 11 insertions(+)
diff --g
On Tue, Apr 23, 2013 at 02:52:18PM -0300, Rodrigo Vivi wrote:
> Display register 42020h bit 9 must be set to 1b for the entire time that
> Frame Buffer Compression is enabled.
>
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8
> 1 file changed, 8 insertions(+)
Display register 42020h bit 9 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_pm.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_p
